X9530 Datasheet, PDF (24/30 Pages) Xicor Inc. – Temperature Compensated Laser Diode Controller

X9530
D/A CONVERTER CHARACTERISTICS
All typical values are for 25°C ambient temperature and 5 V at pin Vcc. Maximum and minimum specifications are over the
recommended operating conditions. All voltages are referred to the voltage at pin Vss unless otherwise specified. All bits in
control registers are “0” unless otherwise specified. 510Ω, 0.1%, resistor connected between R1 and Vss, and another
between R2 and Vss unless otherwise specified. 400kHz TTL input at SCL unless otherwise specified. SDA pulled to Vcc
through an external 2kΩ resistor unless otherwise specified. 2-wire interface in “standby” (see notes 1 and 2 on page 22),
unless otherwise specified. WP, A0, A1, and A2 floating unless otherwise specified.
Symbol
Parameter
Min Typ Max Unit Test Conditions / Notes
IFS₀₀
IFS₀₁
IFS₁₀
I1 or I2 full scale current, with external 1.56 1.58 1.6 mA DAC input Byte = FFh,
resistor setting
Source or sink mode, V(I1)
I1 or I2 full scale current, with internal 0.3 0.4
0.5 mA ^{and V(I2) are Vcc - 1.2V in}
low current setting option
source mode and 1.2V in sink
mode.
I1 or I2 full scale current, with internal
middle current setting option
0.64 0.85
1.06
mA _{See notes 1 and 2.}
IFS₁₁
I1 or I2 full scale current, with internal
high current setting option
1 1.3
1.6 mA
Offset_DAC I1 or I2 D/A converter offset error
1
FSError_DAC I1 or I2 D/A converter full scale error
-2
DNL_DAC
I1 or I2 D/A converter
-0.5
Differential Nonlinearity
1
LSB
2
LSB
0.5 LSB
INL_DAC
I1 or I2 D/A converter Integral Nonlin-
-1
earity with respect to a straight line
through 0 and the full scale value
1
LSB
VISink
I1 or I2 Sink Voltage Compliance
1.2
Vcc
V In this range the current at I1
or I2 vary < 1%
VISource
I1 or I2 Source Voltage Compliance
0
Vcc-1.2 V In this range the current at I1
or I2 vary < 1%
I_OVER
I_UNDER
t_rDAC
I1 or I2 overshoot on D/A Converter
data byte transition
I1 or I2 undershoot on D/A Converter
data byte transition
I1 or I2 rise time on D/A Converter data 5
byte transition; 10% to 90%
0
µA DAC input byte changing from
00h to FFh and vice
0
µA
versa, V(I1) and V(I2) are
Vcc - 1.2V in source mode
and 1.2V in sink mode.
30
µs _{See note 3.}
TCO_I1I2
Temperataure coefficient of output
current I1 or I2 when using internal
resistor setting
±200
ppm/
°C
See Figure 5.
Bits I1FSO[1:0] ¦ 00₂ or
Bits I2FSO[1:0] ¦ 002,
VRMbit = “1”
[ ] Notes: 1. LSB is defined as
2
3
x
V(VRef)
255
divided by the resistance between R1 or R2 to Vss.
2. Offset_DAC: The Offset of a DAC is defined as the deviation between the measured and ideal output, when the DAC input is 01h. It is
expressed in LSB.
FSError_DAC: The Full Scale Error of a DAC is defined as the deviation between the measured and ideal output, when the input is FFh. It
is expressed in LSB. The Offset_DAC is subtracted from the measured value before calculating FSError_DAC.
DNL_DAC: The Differential Non-Linearity of a DAC is defined as the deviation between the measured and ideal incremental change in
the output of the DAC, when the input changes by one code step. It is expressed in LSB. The measured values are adjusted for Offset
and Full Scale Error before calculating DNL_DAC.
INL_DAC: The Integral Non-Linearity of a DAC is defined as the deviation between the measured and ideal transfer curves, after adjust-
ing the measured transfer curve for Offset and Full Scale Error. It is expressed in LSB.
3. These parameters are periodically sampled and not 100% tested.
24
FN8211.0
March 10, 2005