KAD5514P Datasheet, PDF (24/32 Pages) List of Unclassifed Manufacturers – 14-bit, 250/210/170/125MSPS A/D Converter

KAD5514P
TABLE 10. POWER DOWN CONTROL
0x25[2:0]
VALUE
POWER DOWN MODE
100
Sleep Mode
Global Device Configuration/Control
ADDRESS 0X71: PHASE_SLIP
When using the clock divider, it’s not possible to determine
the synchronization of the incoming and divided clock
phases. This is particularly important when multiple ADCs
are used in a time-interleaved system. The phase slip
feature allows the rising edge of the divided clock to be
advanced by one input clock cycle when in CLK/4 mode, as
shown in Figure 40. Execution of a phase_slip command is
accomplished by first writing a ‘0’ to bit 0 at address 71h
followed by writing a ‘1’ to bit 0 at address 71h (32 sclk
cycles ).
CLK = CLKP – CLKN
CLK
CLK÷4
CLK÷4
SLIP ONCE
1.00ns
4.00ns
CLK÷4
SLIP TWICE
FIGURE 40. PHASE SLIP: CLK÷4 MODE, f_CLOCK = 1000MHz
ADDRESS 0X72: CLOCK_DIVIDE
The KAD5514P has a selectable clock divider that can be
set to divide by four, two or one (no division). By default, the
tri-level CLKDIV pin selects the divisor (refer to “Clock Input”
on page 18). This functionality can be overridden and
controlled through the SPI, as shown in Table 11. This
register is not changed by a Soft Reset.
TABLE 11. CLOCK DIVIDER SELECTION
0x72[2:0]
VALUE
CLOCK DIVIDER
000
Pin Control
001
Divide by 1
010
Divide by 2
100
Divide by 4
ADDRESS 0X73: OUTPUT_MODE_A
The output_mode_A register controls the physical output
format of the data, as well as the logical coding. The
KAD5514P can present output data in two physical formats:
LVDS or LVCMOS. Additionally, the drive strength in LVDS
mode can be set high (3mA) or low (2mA). By default, the
tri-level OUTMODE pin selects the mode and drive level (refer
to “Digital Outputs” on page 19). This functionality can be
overridden and controlled through the SPI, as shown in
Table 12.
Data can be coded in three possible formats: two’s
complement, Gray code or offset binary. By default, the
tri-level OUTFMT pin selects the data format (refer to “Data
Format” on page 20). This functionality can be overridden
and controlled through the SPI, as shown in Table 13.
This register is not changed by a Soft Reset.
TABLE 12. OUTPUT MODE CONTROL
0x93[7:5]
VALUE
OUTPUT MODE
000
Pin Control
001
LVDS 2mA
010
LVDS 3mA
100
LVCMOS
TABLE 13. OUTPUT FORMAT CONTROL
0x93[2:0]
VALUE
OUTPUT FORMAT
000
Pin Control
001
Two’s Complement
010
Gray Code
100
Offset Binary
ADDRESS 0X74: OUTPUT_MODE_B
ADDRESS 0X75: CONFIG_STATUS
Bit 6 DLL Range
This bit sets the DLL operating range to fast (default) or
slow.
Bit 4 DDR Enable
Setting this bit enables Double Data-Rate mode.
Internal clock signals are generated by a delay-locked loop
(DLL), which has a finite operating range. Table 15 shows
the allowable sample rate ranges for the slow and fast
settings.
DLL RANGE
Slow
Fast
TABLE 14. DLL RANGES
MIN
MAX
40
100
80
f_{S MAX}
UNIT
MSPS
MSPS
The output_mode_B and config_status registers are used in
conjunction to enable DDR mode and select the frequency
range of the DLL clock generator. The method of setting
these options is different from the other registers.
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FN6804.1
March 4, 2009