KAD5514P Datasheet, PDF (19/32 Pages) List of Unclassifed Manufacturers – 14-bit, 250/210/170/125MSPS A/D Converter

KAD5514P
Jitter
In a sampled data system, clock jitter directly impacts the
achievable SNR performance. The theoretical relationship
between clock jitter (t_J) and SNR is shown in Equation 1 and
is illustrated in Figure 32.
SNR
=
20
log₁₀
⎛
⎝
2^----π^----f^-1-_I^--_N^----t^--_J^{-⎠⎞}
(EQ. 1)
100
95
90
85
80
75
70
65
60
55
50
1
tj = 0.1ps
tj = 1ps
14 BITS
12 BITS
tj = 10ps
tj = 100ps
10 BITS
10
100
INPUT FREQUENCY (MHz)
FIGURE 32. SNR vs CLOCK JITTER
1000
This relationship shows the SNR that would be achieved if
clock jitter were the only non-ideal factor. In reality,
achievable SNR is limited by internal factors such as
linearity, aperture jitter and thermal noise. Internal aperture
jitter is the uncertainty in the sampling instant shown in
Figure 1. The internal aperture jitter combines with the input
clock jitter in a root-sum-square fashion, since they are not
statistically correlated, and this determines the total jitter in
the system. The total jitter, combined with other noise
sources, then determines the achievable SNR.
Voltage Reference
A temperature compensated voltage reference provides the
reference charges used in the successive approximation
operations. The full-scale range of each A/D is proportional
to the reference voltage. The voltage reference is internally
bypassed and is not accessible to the user.
Digital Outputs
Output data is available as a parallel bus in
LVDS-compatible or CMOS modes. Additionally, the data
can be presented in either double data rate (DDR) or single
data rate (SDR) formats. The even numbered output bits are
active in DDR mode. When CLKOUT is low the MSB and all
odd bits are output, while on the high phase the LSB and all
even bits are presented. Figures 1 and 2 show the timing
relationships for LVDS/CMOS and DDR/SDR modes.
The 48-QFN package option contains six LVDS data
outputs, and therefore can only support DDR mode.
Additionally, the drive current for LVDS mode can be set to a
nominal 3mA or a power-saving 2mA. The lower current
setting can be used in designs where the receiver is in close
physical proximity to the ADC. The applicability of this setting
is dependent upon the PCB layout, therefore the user should
experiment to determine if performance degradation is
observed.
The output mode and LVDS drive current are selected via
the OUTMODE pin as shown in Table 2.
TABLE 2. OUTMODE PIN SETTINGS
OUTMODE PIN
MODE
AVSS
LVCMOS
Float
LVDS, 3mA
AVDD
LVDS, 2mA
The output mode can also be controlled through the SPI
port, which overrides the OUTMODE pin setting. Details on
this are contained in the “Serial Peripheral Interface” on
page 20.
An external resistor creates the bias for the LVDS drivers. A
10kΩ, 1% resistor must be connected from the RLVDS pin to
OVSS.
Over-Range Indicator
The over-range (OR) bit is asserted when the output code
reaches positive full-scale (e.g. 0xFFF in offset binary mode).
The output code does not wrap around during an over-range
condition. The OR bit is updated at the sample rate.
Power Dissipation
The power dissipated by the KAD5514P is primarily
dependent on the sample rate and the output modes: LVDS
vs CMOS and DDR vs. SDR. There is a static bias in the
analog supply, while the remaining power dissipation is
linearly related to the sample rate. The output supply
dissipation changes to a lesser degree in LVDS mode, but is
more strongly related to the clock frequency in CMOS mode.
Nap/Sleep
Portions of the device may be shut down to save power
during times when operation of the ADC is not required. Two
power saving modes are available: Nap, and Sleep. Nap
mode reduces power dissipation by approximately 65% and
recovers to normal operation in approximately 1µs. Sleep
mode reduces power dissipation to less than 18mW but
requires 1ms to recover.
All digital outputs (Data, CLKOUT and OR) are placed in a
high impedance state during Nap or Sleep. The input clock
should remain running and at a fixed frequency during Nap
or Sleep. Recovery time from Nap mode will increase if the
clock is stopped, since the internal DLL can take up to 52µs
to regain lock at 250MSPS.
By default after the device is powered on, the operational
state is controlled by the NAPSLP pin as shown in Table 3.
19
FN6804.1
March 4, 2009