ISLA212P Datasheet, PDF (22/35 Pages) Intersil Corporation – 12-Bit, 250MSPS/200MSPS/130MSPS ADC

ISLA212P
Data Format
Output data can be presented in three formats: two’s
complement (default), Gray code and offset binary. The data
format can be controlled through the SPI port, by writing to
address 0x73. Details on this are contained in “Serial Peripheral
Interface” on page 25.
Offset binary coding maps the most negative input voltage to
code 0x000 (all zeros) and the most positive input to 0xFFF (all
ones). Two’s complement coding simply complements the MSB
of the offset binary representation.
When calculating Gray code the MSB is unchanged. The
remaining bits are computed as the XOR of the current bit
position and the next most significant bit. Figure 33 shows this
operation.
BINARY
11 10 9 • • • •
10
Converting back to offset binary from Gray code must be done
recursively, using the result of each bit for the next lower bit as
shown in Figure 34.
GRAY CODE
11 10
9
••••
1
0
••••
••••
••••
GRAY CODE
11 10 9
•••• 1 0
FIGURE 33. BINARY TO GRAY CODE CONVERSION
BINARY
11 10
9
•••• 1 0
FIGURE 34. GRAY CODE TO BINARY CONVERSION
Mapping of the input voltage to the various data formats is
shown in Table 3.
TABLE 3. INPUT VOLTAGE TO OUTPUT CODE MAPPING
INPUT
VOLTAGE
OFFSET BINARY
TWO’S
COMPLEMENT
GRAY CODE
–Full Scale 0000 0000 0000 1000 0000 0000 0000 0000 0000
–Full Scale 0000 0000 0001 1000 0000 0001 0000 0000 0001
+ 1LSB
Mid–Scale 1000 0000 0000 0000 0000 0000 1100 0000 0000
+Full Scale 1111 1111 1110 0111 1111 1110 1000 0000 0001
– 1LSB
+Full Scale 1111 1111 1111 0111 1111 1111 1000 0000 0000
Clock Divider Synchronous Reset
An output clock (CLKOUTP, CLKOUTN) is provided to facilitate
latching of the sampled data. This clock is at half the frequency
of the sample clock, and the absolute phase of the output clocks
for multiple A/Ds is indeterminate. This feature allows the phase
of multiple A/Ds to be synchronized (see Figure35), which greatly
simplifies data capture in systems employing multiple A/Ds.
The reset signal must be well-timed with respect to the sample
clock (See “Switching Specifications” on page 13).
22
FN7717.1
May 11, 2011