ISLA212P Datasheet, PDF (14/35 Pages) Intersil Corporation – 12-Bit, 250MSPS/200MSPS/130MSPS ADC

ISLA212P
Switching Specifications Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
PARAMETER
SYMBOL
CONDITION
MIN
MAX
(Note 5)
TYP
(Note 5)
UNITS
Overvoltage Recovery
t_OVR
1
cycles
SPI INTERFACE (Notes 13, 14)
SCLK Period
t
CLK
Write Operation
16
cycles
t_CLK
Read Operation
16
cycles
CSB↓ to SCLK↑ Setup Time
t_S
Read or Write
28
cycles
CSB↑ after SCLK↑ Hold Time
t_H
Write
5
cycles
CSB↑ after SCLK↓ Hold Time
t_HR
Read
16
cycles
Data Valid to SCLK↑ Setup Time
t_DS
Write
6
cycles
Data Valid after SCLK↑ Hold Time
t_DH
Read or Write
4
cycles
Data Valid after SCLK↓ Time
t_DVR
Read
5
cycles
NOTES:
12. The relative propagation delay is the difference in propagation time between any two devices that are matched in temperature and voltage, and is
specified over the full operating temperature and voltage range.
13. SPI Interface timing is directly proportional to the ADC sample period (t_S). Values above reflect multiples of a 4ns sample period, and must be scaled
proportionally for lower sample rates. ADC sample clock must be running for SPI communication.
14. The SPI may operate asynchronously with respect to the ADC sample clock.
Typical Performance Curves
All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V, T_A = +25°C,
A_IN = -1dBFS, f_IN = 105MHz, f_SAMPLE = 250MSPS.
95
-60
90
SFDR @ 130MSPS
85
SFDR @ 250MSPS
-65
HD2 @ 250MSPS
-70
-75
HD3 @ 250MSPS
80
-80
75
70
65 _{SNR @ 250MSPS}
SNR @ 130MSPS
60
0
100
200
300
400
500
600
INPUT FREQUENCY (MHz)
FIGURE 3. SNR AND SFDR vs f_IN
-85
-90
-95
HD3 @ 130MSPS ^{HD2 @ 130MSPS}
-100
-105
0
100
200
300
400
500
600
INPUT FREQUENCY (MHz)
FIGURE 4. HD2 AND HD3 vs f_IN
14
FN7717.1
May 11, 2011