ISL78171 Datasheet, PDF (21/29 Pages) Intersil Corporation – 6-Channel, 50mA Automotive LED Driver with Ultra-high Dimming Ratio and Phase Shift Control

ISL78171
PWM Brightness Control Register (0x00)
The brightness control resolution has 256 steps of PWM duty cycle
adjustment. Figure 34 shows the bit assignment. All of the bits in
this Brightness Control Register can be read or written. Step 0
corresponds to the minimum step where the current is less than
10µA. Steps 1 to 255 represent the linear steps between 0.39% and
100% duty cycle with approximately 0.39% duty cycle adjustment
per step.
• An SMBus/I²C Write Byte cycle to Register 0x00 sets the PWM
brightness level only if the backlight controller is in SMBus/I²C
mode (see Table 4) Operating Modes selected by Device
Control Register Bits 1 and 2).
• An SMBus/I²C Read Byte cycle to Register 0x00 returns the
programmed PWM brightness level.
• An SMBus/I²C setting of 0xFF for Register 0x00 sets the
backlight controller to the maximum brightness.
• An SMBus/I²C setting of 0x00 for Register 0x00 sets the
backlight controller to the minimum brightness output.
• Default value for Register 0x00 is 0xFF.
Device Control Register (0x01)
This register has two bits that control either SMBus/I²C
controlled or external PWM controlled PWM dimming and a
single bit that controls the backlight ON/OFF state. The
remaining bits are reserved. The bit assignment is shown in
Figure 35. All other bits in the Device Control Register will read as
low unless otherwise written.
• All reserved bits have no functional effect when written.
• All defined control bits return their current, latched value when
read.
A value of 1 written to BL_CTL turns on the backlight in 4ms or less
after the write cycle completes. The backlight is deemed to be on
when Bit 3 BL_STAT of Register 0x02 is 1 and Register 0x09 is not 0.
A value of 0 written to BL_CTL immediately turns off the BL. The
BL is deemed to be off when Bit 3 BL_STAT of Register 0x02 is 0
and Register 0x09 is 0.
The default value for Register 0x01 is 0x00.
REGISTER 0x00
PWM BRIGHTNESS CONTROL REGISTER
BRT7
BRT6
BRT5
BRT4
BRT3
BRT2
BRT1
BRT0
Bit 7 (R/W) Bit 6 (R/W) Bit 5 (R/W) Bit 4 (R/W) Bit 3 (R/W) Bit 2 (R/W) Bit 1 (R/W) Bit 0 (R/W)
BIT ASSIGNMENT
BRT[7..0]
BIT FIELD DEFINITIONS
= 256 steps of PWM brightness levels
FIGURE 34. DESCRIPTIONS OF BRIGHTNESS CONTROL REGISTER
REGISTER 0x01
DEVICE CONTROL REGISTER
RESERVED
Bit 7 (R/W)
RESERVED
Bit 6 (R/W)
RESERVED
Bit 5 (R/W)
RESERVED
Bit 4 (R/W)
RESERVED
Bit 3 (R/W)
PWM_MD PWM_SEL BL_CTL
Bit 2 (R/W) Bit 1 (R/W) Bit 0 (R/W)
PWM_MD
X
0
1
X
PWM_SEL
X
0
0
1
BL_CTL
0
1
1
1
MODE
Backlight Off
SMBus/I²C and PWM input controlled Display Power Saving Technology (DPST)
dimming (Method 3, PWMI x PWM Reg & FPWM)
SMBus/I²C controlled PWM dimming (Method 1, PWM Reg & FPWM)
PWM input controlled PWM dimming (Method 2, PWMI & FPWM)
FIGURE 35. DESCRIPTIONS OF DEVICE CONTROL REGISTER
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FN8602.0
June 15, 2015