ISL78171 Datasheet, PDF (13/29 Pages) Intersil Corporation – 6-Channel, 50mA Automotive LED Driver with Ultra-high Dimming Ratio and Phase Shift Control

ISL78171
3. Display Power Saving Technology (DPST) mode: The PWM
dimming frequency is set by the resistor on FPWM pin & duty
cycle is the product of the duty set by the 256 bit PWM
brightness register (BRT) through PMBus/I²C and the duty
cycle information from the external PWM input signal.
4. Direct PWM mode: In this case the output duty cycle and
dimming frequency follows the input PWM signal. This is
purely an analog dimming method for use when the
PMBus/I²C controls are not needed.
The default PWM dimming mode is in Display Power Saving
Technology (DPST). In all of the methods, the average LED
channel current is controlled by I_LED and the PWM duty cycle in
percent, as shown in Equation 5:
I_{LEDave} = I_LED  PWM
(EQ. 5)
Method 1 (SMBus/I²C Controlled Dimming)
The average LED channel current is controlled by the internally
generated PWM signal, as shown in Equation 6:
I_{LEDave} = I_LED  BRT  255
(EQ. 6)
Where BRT is the value programmed in the PWM brightness
Register 0x00. BRT ranges from 0 to 255 in decimal and defaults
to 255 (0xFF). BRT = 0 disconnects all channels.
Setting the Control Register 0x01 to 0x05 programs the device to
use only the SMBus/I²C controlled PWM brightness control.
Alternatively, the same operation can be obtained by setting
Register 0x01 at its default value of 0x01 Display Power Saving
Technology (DPST) and connecting the PWM input to VDC, so that
the dimming level depends only on the BRT register.
The PWM dimming frequency is adjusted by a resistor at the
FPWM pin.
Method 2 (PWM Controlled Dimming with Settable Dimming
Frequency)
The average LED channel current is controlled by the duty cycle of
external PWM signal, as shown in Equation 7:
I_{LILEDave} = I_LED  PWMI
(EQ. 7)
The PWM dimming frequency is adjusted by a resistor at the
FPWM pin. The PWM input cannot be low for more than 30.5ms
or else the driver will enter shutdown.
Setting the Control Register 0x01 to 0x03 programs the device to
use the duty of the externally applied PWM signal for brightness
control. Alternatively, the same operation can be obtained by
leaving Register 0x01 at its default value of 0x01 Display Power
Saving Technology (DPST), and not program Register BRT, so that
it contains its default value of 0xFF.
Method 3 Display Power Saving Technology (DPST).
The average LED channel current can also be controlled by the
product of the SMBus/I²C controlled PWM and the external PWM
signals as:
I_{LEDave} = I_LEDxPWM_DPST
(EQ. 8)
Where:
PPWM_DPST = BRT  255  PWMI
(EQ. 9)
Therefore:
I_{LEDave} = I_LED  BRT  255  PWMI
(EQ. 10)
Where BRT is the value held in PWM Register 0x00 (default
setting 0xFF) controlled by SMBus/I²C and PWMI is the duty
cycle of the incoming external PWM signal. In this way, the users
can change the PWM current in ratio metric manner to achieve
Display Power Saving Technology (DPST) compliant backlight
dimming. To use the Display Power Saving Technology (DPST)
mode, users need to set the control Register 0x01 to 0x01. The
PWM dimming frequency is adjusted by a resistor at the FPWM
pin.
For example, if the SMBus/I²C controlled PWM duty is 80%
dimming at 200Hz (see Equation 11) and the external PWM duty
cycle is 60% dimming at 1kHz, the resultant PWM duty cycle is
48% dimming at 200Hz.
In Display Power Saving Technology (DPST) mode, the ISL78171
features 8-bit dimming resolution. The product of the PWMI duty
cycle, (digitized with 8-bit resolution) and of the BRT I²C register,
results in a 16 bit value.The device calculates the dimming level
by taking the 8 most significant bits of the 16 bit result.
Method 4 (Direct PWM Mode)
Direct PWM Dimming mode is selected when F_PWM is tied to V_DC
and SMBCLK/SMBDAT are grounded. The current of the six LED
channels will follow the External PWM signal’s frequency and
duty cycle. The minimum duty cycle can be as low as 0.007% at
200Hz (or equivalent pulse width of 350ns). This ultra low duty
cycle dimming performance can be achieved if no channel
capacitor is present. Also, in Direct PWM Dimming mode the
Phase Shift function will be disabled.
TABLE 1. DIMMING MODE SELECTION
DIMMING
METHOD
SELECTION
SMBCLK/ SMBDAT/
SCL PIN SDA PIN FPWM
SIGNAL SIGNAL PIN
0x01 REGISTER
Method 1
SMBUS/
(SMBUS/I²C
I²C clock
controlled dimming,
PWM Reg for Duty and
FPWM for Frequency)
SMBUS/
I²C data
Resistor Set to 0x05, or set
to ground to 0x01 and
connect PWM to
VDC
Method 2
(PWMI for Duty &
FPWM for Frequency)
SMBUS/
I²C clock
SMBUS/
I²C data
Resistor Set to 0x03, or set
to ground to 0x01 and not
program register
0x00
Method 2
Grounded Grounded Resistor N/A
(PWMI for Duty &
to ground
FPWM for Frequency)
Method 3
SMBUS/
Display Power Saving I²C clock
Technology (DPST),
Product of PWMI &
PWM Reg for Duty and
FPWM for Frequency
SMBUS/
I²C data
Resistor Set to 0x01
to ground
Method 4
Grounded Grounded Tie to N/A
(Direct PWM dimming,
VDC
PWMI for Duty and
Frequency)
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June 15, 2015