ISL6256 Datasheet, PDF (21/26 Pages) Intersil Corporation – Highly Integrated Battery Charger with Automatic Power Source Selector for Notebook Computers

ISL6256, ISL6256A
PHASE
L
11
R _{FET_rDS(ON)}
R_{L_DCR}
:
60
40
f_ZERO
COMPENSATOR
MODULATOR
LOOP
+
Σ
0.25
-
ICOMP
C_ICOMP
-
gm2
+
+
20
-
CA2
CSOP
CSON
CHLIM
+
-
R_F2
C _F2
R_S2
CO
R_ESR
R_BAT
FIGURE 19. CHARGE CURRENT LIMIT LOOP
The compensation capacitor (C_ICOMP) gives the error
amplifier (GMI) a pole at a very low frequency (<<1Hz) and a
a zero at f_Z1. f_Z1 is created by the 0.25*CA2 output added to
ICOMP. The frequency of can be calculated from Equation 33.
f_ZERO
=
----------⁴-----^â‹---^g----^m-----²------------
(2π ⋅ C_ICOMP)
gm2 = 50μA ⁄ V
(EQ. 33)
Placing this zero at a frequency equal to the pole calculated
in Equation 31 will result in maximum gain at low frequencies
and phase margin near 90°. If the zero is at a higher
frequency (smaller C_ICOMP), the DC gain will be higher but
the phase margin will be lower. Use a capacitor on ICOMP
that is equal to or greater than the value calculated in
Equation 34:
C_ICOMP = ₍---_R-----_S---₂-----+-----_r--_D----_S-⁴---₍--^â‹_O---⁽--_N⁵----⁰₎---+^μ----^A-_R-----_D^⁄--^V--_C---⁾-_R-----+-----_R-----_B----_A----_T---₎
(EQ. 34)
A filter should be added between R_S2 and CSOP and CSON
to reduce switching noise. The filter roll off frequency should
be between the crossover frequency and the switching
frequency (~100kHz). R_F2 should be small (<10Ω) to
minimize offsets due to leakage current into CSOP. The filter
cut off frequency is calculated using Equation 35:
f_FILTER
=
--------------------¹----------------------
(2π ⋅ C_F2 ⋅ R_F2)
(EQ. 35)
The crossover frequency is determined by the DC gain of the
modulator and output filter and the pole in Equation 31. The
DC gain is calculated in Equation 36 and the crossover
frequency is calculated with Equation 37.
A_DC = ₍---_R-----_S---₂-----+-----_r--_D----_S----₍--_O-----_N----₎¹---+-¹----_R-^â‹---^R-_D---^S-_C---²-_R-----+-----_R-----_B----_A---_T----_T----_E----_R----_Y----₎
(EQ. 36)
f_CO = A_DC ⋅ f_POLE1 = ¹----¹²----_π-^â‹---^R-_â‹---_L^S----²-
(EQ. 37)
The Bode plot of the loop gain, the compensator gain and
the power stage gain is shown in Figure 20.
20
0
-20
f_POLE1
f_FILTER
-40
f_POLE2
-60
0.01k
0.1k
1k
10k
100k
1M
FREQUENCY (Hz)
FIGURE 20. CHARGE CURRENT LOOP BODE PLOTS
Adapter Current Limit Control Loop
If the combined battery charge current and system load
current draws current that equals the adapter current limit
set by the ACLIM pin, ISL6256 will reduce the current to the
battery and/or reduce the output voltage to hold the adapter
current at the limit. Above the adapter current limit, the
minimum current buffer equals the output of gm3 and
ICOMP controls the charger output. Figure 21 shows the
adapter current limit control loop.
.
DCIN
R_S1
R_F1
PHASE
L
11
R _{FET_rDS(ON)}
R_{L_DCR}
C_F1
Σ
CSIN
CSIP
ICOMP
C_ICOMP
+
0.25
-
- ₂₀
+
CA1
+
20
-
CA2
CSOP
CSON
-
gm3
+
ACLIM +
-
R_F2
C_F2
R
C_O
R_ESR
FIGURE 21. ADAPTER CURRENT LIMIT LOOP
The loop response equations, bode plots and the selection
of C_ICOMP are the same as the charge current control loop
with loop gain reduced by the duty cycle and the ratio of
R_S1/R_S2. In other words, if R_S1= R_S2 and the duty cycle
D = 50%, the loop gain will be 6dB lower than the loop gain
in Figure 21. This gives lower crossover frequency and
higher phase margin in this mode. If R_S1/R_S2 = 2 and the
duty cycle is 50% then the adapter current loop gain will be
identical to the gain in Figure 21.
21
FN6499.3
September 14, 2010