HI7190_06 Datasheet, PDF (21/25 Pages) Intersil Corporation – 24-Bit, High Precision, Sigma Delta A/D Converter

HI7190
Changing the filter notch frequency, as well as the selected
gain, impacts resolution. The output data rate (or effective
conversion time) for the device is equal to the frequency
selected for the first notch to the filter. For example, if the
first notch of the filter is selected at 50Hz then a new word is
available at a 50Hz rate or every 20ms. If the first notch is at
1kHz a new word is available every 1ms.
The settling-time of the converter to a full scale step input
change is between 3 and 4 times the data rate. For example,
with the first filter notch at 50Hz, the worst case settling time
to a full scale step input change is 80ms. If the first notch is
1kHz, the settling time to a full scale input step is 4ms
maximum.
The -3dB frequency is determined by the programmed first
notch frequency according to the relationship:
f _-3dB = 0.262 x f_NOTCH.
MD2 through MD0 - Bits 11 through 9 are the Operational
Modes of the converter. See Table 4 for the Operational
Modes description. After a RESET is applied to the part
these bits are set to the self calibration mode.
B/U - Bit 8 is the Bipolar/Unipolar select bit. When this bit is
set the HI7190 is configured for bipolar operation. When this
bit is reset the part is in unipolar mode. This bit is set after a
RESET is applied to the part.
G2 through G0 - Bits 7 through 5 select the gain of the input
analog signal. The gain is accomplished through a
programmable gain instrumentation amplifier that gains up
incoming signals from 1 to 8. This is achieved by using a
switched capacitor voltage multiplier network preceding the
modulator. The higher gains (i.e., 16 to 128) are achieved
through a combination of a PGIA gain of 8 and a digital
multiply after the digital filter (see Table 7). The gain will
affect noise and Signal to Noise Ratio of the conversion.
These bits are cleared to a gain of 1 (G2, G1, G0 = 000) after
a RESET is applied to the part.
TABLE 7. GAIN SELECT BITS
G2 G1 G0 GAIN
GAIN ACHIEVED
0
0
0
1 PGIA = 1, Filter Multiply = 1
0
0
1
2 PGIA = 2, Filter Multiply = 1
0
1
0
4 PGIA = 4, Filter Multiply = 1
0
1
1
8 PGIA = 8, Filter Multiply = 1
1
0
0
16 PGIA = 8, Filter Multiply = 2
1
0
1
32 PGIA = 8, Filter Multiply = 4
1
1
0
64 PGIA = 8, Filter Multiply = 8
1
1
1
128 PGIA = 8, Filter Multiply = 16
BO - Bit 4 is the Transducer Burn-Out Current source enable
bit. When this bit is set (BO = 1) the burn-out current source
connected to V_INHI internally is enabled. This current source
can be used to detect the presence of an external
connection to V_INHI. This bit is cleared after a RESET is
applied to the part.
SB - Bit 3 is the Standby Mode enable bit used to put the
HI7190 in a lower power/standby mode. When this bit is set
(SB = 1) the filter nodes are halted, the DRDY line is set high
and the modulator clock is disabled. When this bit is cleared
the HI7190 begins operation as described by the contents of
the Control Register. For example, if the Control Register is
programmed for Self Calibration Mode and a notch
frequency to 10Hz, the HI7190 will perform the self
calibration before providing the data at the 10Hz rate. This
bit is cleared after a RESET is applied to the part.
BD - Bit 2 is the Byte Direction bit used to select the multi-
byte access ordering. The bit determines the either
ascending or descending order access for the multi-byte
registers. When set (BD = 1) the user can access multi-byte
registers in ascending byte order and when cleared (BD = 0)
the multi-byte registers are accessed in descending byte
order. This bit is cleared after a RESET is applied to the part.
MSB - Bit 1 is used to select whether a serial data transfer is
MSB or LSB first. This bit allows the user to change the
order that data can be transmitted or received by the
HI7190. When this bit is cleared (MSB = 0) the MSB is the
first bit in a serial data transfer. If set (MSB = 1), the LSB is
the first bit transferred in the serial data stream. This bit is
cleared after a RESET is applied to the part.
SDL - Bit 0 is the Serial Data Line control bit. This bit selects
the transfer protocol of the serial interface. When this bit is
cleared (SDL = 0), both read and write data transfers are
done using the SDIO line. When set (SDL = 1), write
transfers are done on the SDIO line and read transfers are
done on the SDO line. This bit is cleared after a RESET is
applied to the part.
Reading the Data Output Register
The HI7190 generates an active low interrupt (DRDY)
indicating valid conversion results are available for reading.
At this time the Data Output Register contains the latest
conversion result available from the HI7190. Data integrity is
maintained at the serial output port but it is possible to miss
a conversion result if the Data Output Register is not read
within a given period of time. Maintaining data integrity
means that if a Data Output Register read of conversion N is
begun but not finished before the next conversion
(conversion N + 1) is complete, the DRDY line remains
active low and the data being read is not overwritten.
In addition to the Data Output Register, the HI7190 has a
one conversion result storage buffer. No conversion results
will be lost if the following constraints are met.
1) A Data Output Register read cycle is started for a given
conversion (conversion X) 1/f_N - (128*1/f_OSC) after DRDY
initially goes active low. Failure to start the read cycle may
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FN3612.10
June 27, 2006