ISL78208_14 Datasheet, PDF (20/24 Pages) Intersil Corporation – Wide VIN Dual Standard Buck Regulator with 3A/3A Continuous Output Current

ISL78208
Vo
R₂
C₃
V _{FB -}
R₃
V _REF
GM
+
V _COMP
R₁
C₂
C₁
FIGURE 47. TYPE II COMPENSATOR
Figure 47 shows the type II compensator and its transfer function
is expressed as Equation 23:
A_vS=
-^vˆ---c_vˆ---^oF---^m-_B----^p- =
-------^g----^m---------
C₁ + C₂
-^--¹-----+------^--------^c-^S-----z-------^{1---}----^--¹-----+------^---------^{cS------z------2----}-
S_1 + _----^S-_c---_p-_
(EQ. 23)
Where:
_cz1
=
-------¹-------
R₁C₁
,
_cz2 =
-_R----₂--¹-_C-----₃- _cp=
--^C----¹-----+----^C-----²--
R₁C₁C₂
(EQ. 24)
the compensator design goal is:
High DC gain
Loop bandwidth f_c:


1_--
4
t
o
1^--1--0^{--}
f
s
Gain margin: >10dB
Phase margin: 40°
The compensator design procedure is shown in Equation 25:
Put compensator zero
_cz1
=

1t
o
3

--------¹---------
R_OC_O
(EQ. 25)
Put one compensator pole at zero frequency to achieve high DC
gain, and put another compensator pole at either ESR zero
frequency or half switching frequency, whichever is lower.
The loop gain T_v(S) at crossover frequency of f_c has unity gain.
Therefore, the compensator resistance R₁ is determined by
Equation 26:
R₁
=
2_----_----f_--c---V_----o----C_----o----R_----T--
g_mV_FB
(EQ. 26)
where g_m is the trans-conductance of the voltage error amplifier,
typically 200µA/V. Compensator capacitor C₁ is then given by
Equation 27:
C₁ = -_R----₁---¹_-----_c---_z- ,C₂= -₂---_----_R----¹-₁---_f--_e---_s---_r
(EQ. 27)
Example: V_IN = 12V, V_o = 5V, I_o = 3A, f_s = 500kHz,
CV_FoB==202.08µVF, /S5_em=_1,.1L=105₅.6Vµ/Hs,, _{Sgnm==32.40}01µ0s₅, _{VR/Ts=, f0c}.=218,0kHz, _then
compensator resistance R₁ = 72k.
Put the compensator zero at 6.6kHz (~1.5x C_oR_o), and put the
compensator pole at ESR zero, which is 1.45MHz. The
compensator capacitors are:
C₁ = 470pF, C₂ = 3pF (There is approximately 3pF parasitic
capacitance from V_COMP to GND; therefore, C₂ is optional).
Figure 48A shows the simulated voltage loop gain. It is shown
that it has 80kHz loop bandwidth with 69° phase margin and
15dB gain margin. Optional addition phase boost can be added
to the overall loop response by using C₃.
60
45
30
GAIN (dB)
15
0
-15
-30100
1•10³
1•10⁴
FIGURE 48A.
1•10⁵
1•10⁶
100
80
60
PHASE (°)
40
20
0
-20
100
1•10³
1•10⁴
FIGURE 48B.
1•10⁵
1•10⁶
Rectifier Selection
Current circulates from ground to the junction of the external
Schottky diode and the inductor when the high-side switch is off.
As a consequence, the polarity of the switching node is negative
with respect to ground. This voltage is approximately -0.5V
(a Schottky diode drop) during the off-time. The rectifier's rated
reverse breakdown voltage must be at least equal to the
maximum input voltage, preferably with a 20% derating factor.
The power dissipation when the Schottky diode conducts is
expressed in Equation 28:
P_DW
=
I_O
U
T

V_D




1
–
V_{----V-O---I-U-N---T--}
(EQ. 28)
Where:
V_D is the voltage drop of the Schottky diode. Selection of the
Schottky diode is critical in terms of the high temperature
reverse bias leakage current which is very dependent on V_IN and
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FN8354.1
July 29, 2014