ISL6566_06 Datasheet, PDF (20/29 Pages) Intersil Corporation – Three-Phase Buck PWM Controller with Integrated MOSFET Drivers for VRM9, VRM10, and AMD Hammer Applications

ISL6566
If VSEN or RGND become opened, VDIFF falls, causing the
duty cycle to increase and the output voltage on IREF to
increase. If the voltage on IREF exceeds “VDIFF+1V”, the
controller will shut down. Once the voltage on IREF falls
below “VDIFF+1V”, the ISL6566 will restart at the beginning
of soft-start.
Overcurrent Protection
The ISL6566 detects overcurrent events by comparing the
droop voltage, V_DROOP, to the OCSET voltage, V_OCSET, as
shown in Figure 13. The droop voltage, set by the external
current sensing circuitry, is proportional to the output current
as shown in Equation 7. A constant 100µA flows through
R_OCSET, creating the OCSET voltage. When the droop
voltage exceeds the OCSET voltage, the overcurrent
protection circuitry activates. Since the droop voltage is
proportional to the output current, the overcurrent trip level,
I_MAX, can be set by selecting the proper value for R_OCSET,
as shown in Equation 14.
R_OCSET
=
I_{--M-----A----X-----}⋅_---R_{-----C----O----M-----P-----}⋅_---D_-----C_-----R_--
100µ ⋅ R_S
(EQ. 14)
Once the output current exceeds the overcurrent trip level,
V_DROOP will exceed V_OCSET, and a comparator will trigger the
converter to begin overcurrent protection procedures. At the
beginning of overcurrent shutdown, the controller turns off both
upper and lower MOSFETs. The system remains in this state
for a period of 4096 switching cycles. If the controller is still
enabled at the end of this wait period, it will attempt a soft-start
(as shown in Figure 14). If the fault remains, the trip-retry cycles
will continue indefinitely until either the controller is disabled or
the fault is cleared. Note that the energy delivered during trip-
retry cycling is much less than during full-load operation, so
there is no thermal hazard.
OUTPUT CURRENT, 50A/DIV
0A
OUTPUT VOLTAGE,
500mV/DIV
0V
2ms/DIV
FIGURE 14. OVERCURRENT BEHAVIOR IN HICCUP MODE
F_SW = 500kHz
General Design Guide
This design guide is intended to provide a high-level
explanation of the steps necessary to create a multi-phase
power converter. It is assumed that the reader is familiar with
many of the basic skills and techniques referenced below. In
addition to this guide, Intersil provides complete reference
designs that include schematics, bills of materials, and example
board layouts for all common microprocessor applications.
Power Stages
The first step in designing a multi-phase converter is to
determine the number of phases. This determination
depends heavily on the cost analysis which in turn depends
on system constraints that differ from one design to the next.
Principally, the designer will be concerned with whether
components can be mounted on both sides of the circuit
board, whether through-hole components are permitted, the
total board space available for power-supply circuitry, and
the maximum amount of load current. Generally speaking,
the most economical solutions are those in which each
phase handles between 25 and 30A. All surface-mount
designs will tend toward the lower end of this current range.
If through-hole MOSFETs and inductors can be used, higher
per-phase currents are possible. In cases where board
space is the limiting constraint, current can be pushed as
high as 40A per phase, but these designs require heat sinks
and forced air to cool the MOSFETs, inductors and heat-
dissipating surfaces.
MOSFETS
The choice of MOSFETs depends on the current each
MOSFET will be required to conduct, the switching frequency,
the capability of the MOSFETs to dissipate heat, and the
availability and nature of heat sinking and air flow.
LOWER MOSFET POWER CALCULATION
The calculation for power loss in the lower MOSFET is
simple, since virtually all of the loss in the lower MOSFET is
due to current conducted through the channel resistance
(r_DS(ON)). In Equation 15, I_M is the maximum continuous
output current, I_PP is the peak-to-peak inductor current (see
Equation 1), and d is the duty cycle (V_OUT/V_IN).
P_{LOW, 1}
=
r_DS(ON)



-I-^M---
N
2
(
1
–
d)
+
-I-^L---^,---^2P----^P----⁽--1-----^–-----d----⁾
12
(EQ. 15)
An additional term can be added to the lower-MOSFET loss
equation to account for additional loss accrued during the
dead time when inductor current is flowing through the
lower-MOSFET body diode. This term is dependent on the
diode forward voltage at I_M, V_D(ON), the switching
frequency, f_S, and the length of dead times, t_d1 and t_d2, at
the beginning and the end of the lower-MOSFET conduction
interval respectively.
P_{LOW, 2}
=
V_D(ON) f_S


I--_M---
N
+
I--_{P--2--P--}
t_d1
+


-I-^M---
N
–
I--_{P----P--}
2
t_d2
(EQ. 16)
The total maximum power dissipated in each lower MOSFET
is approximated by the summation of P_LOW,1 and P_LOW,2.
20
FN9178.4
March 9, 2006