ISL6566_06 Datasheet, PDF (18/29 Pages) Intersil Corporation – Three-Phase Buck PWM Controller with Integrated MOSFET Drivers for VRM9, VRM10, and AMD Hammer Applications

ISL6566
ISL6566 INTERNAL CIRCUIT _{EXTERNAL CIRCUIT}
POR
CIRCUIT
VCC
PVCC1
+12V
ENABLE
COMPARATOR
+
-
10.7kΩ
ENLL
1.40kΩ
0.66V
SOFT-START
AND
FAULT LOGIC
FIGURE 11. POWER SEQUENCING USING THRESHOLD-
SENSITIVE ENABLE (ENLL) FUNCTION
2. The voltage on ENLL must be above 0.66V. The ENLL
input allows for power sequencing between the controller
bias voltage and another voltage rail. The enable
comparator holds the ISL6566 in shutdown until the
voltage at ENLL rises above 0.66V. The enable
comparator has 60mV of hysteresis to prevent bounce.
3. The driver bias voltage applied at the PVCC pins must
reach the internal power-on reset (POR) rising threshold.
In order for the ISL6566 to begin operation, PVCC1 is the
only pin that is required to have a voltage applied that
exceeds POR. However, for 2 or 3-phase operation
PVCC2 and PVCC3 must also exceed the POR
threshold. Hysteresis between the rising and falling
thresholds assure that once enabled, the ISL6566 will not
inadvertently turn off unless the PVCC bias voltage drops
substantially (see Electrical Specifications).
4. The VID code must not be 111111 or 111110 in VRM10
mode or 11111 in AMD Hammer or VRM9 modes. These
codes signal the controller that no load is present. The
controller will enter shut-down mode after receiving either
of these codes and will execute soft-start upon receiving
any other code. These codes can be used to enable or
disable the controller but it is not recommended. After
receiving one of these codes, the controller executes a
2-cycle delay before changing the overvoltage trip level to
the shut-down level and disabling PWM. Overvoltage
shutdown cannot be reset using one of these codes.
When each of these conditions is true, the controller
immediately begins the soft-start sequence.
SOFT-START
The soft-start function allows the converter to bring up the
output voltage in a controlled fashion, resulting in a linear
ramp-up. Following a delay of 16 PHASE clock cycles
between enabling the chip and the start of the ramp, the
output voltage progresses at a fixed rate of 12.5mV per each
16 PHASE clock cycles.
Thus, the soft-start period (not including the 16 PHASE clock
cycle delay) up to a given voltage, V_DAC, can be
approximated by the following equation
T_SS
=
V_{-----D----A----C-----}⋅_---1_----2_---8_---0_--
f_S
(EQ. 13)
where V_DAC is the DAC-set VID voltage, and f_S is the
switching frequency.
The ISL6566 also has the ability to start up into a pre-
charged output, without causing any unnecessary
disturbance. The FB pin is monitored during soft-start, and
should it be higher than the equivalent internal ramping
reference voltage, the output drives hold both MOSFETs off.
Once the internal ramping reference exceeds the FB pin
potential, the output drives are enabled, allowing the output
to ramp from the pre-charged level to the final level dictated
by the DAC setting. Should the output be pre-charged to a
level exceeding the DAC setting, the output drives are
enabled at the end of the soft-start period, leading to an
abrupt correction in the output voltage down to the DAC-set
level.
OUTPUT PRECHARGED
ABOVE DAC LEVEL
OUTPUT PRECHARGED
BELOW DAC LEVEL
GND>
V_OUT (0.5V/DIV)
GND>
ENLL (5V/DIV)
T1 T2
T3
FIGURE 12. SOFT-START WAVEFORMS FOR ISL6566-BASED
MULTI-PHASE CONVERTER
18
FN9178.4
March 9, 2006