ISL6295 Datasheet, PDF (20/25 Pages) Intersil Corporation – Low Voltage Fuel Gauge

ISL6295
OPERATION MODE CONTROL REGISTER - OPmode
(Address 7A Hex/122 Decimal)
7
6
543
2
1
0
SSLP RESERVED SSLPdiv SHELF POR sPOR
SSLP
Sample-Sleep Mode enable: Setting this bit to
‘1’ immediately enables Sample-Sleep Mode.
Clearing this bit immediately disables Sample-
Sleep mode.
Reserved Reserved bit.
SSLPdiv
Sample-Sleep Divider setting: Sets the interval
between executing an A/D conversion cycle
during Sample-Sleep mode. The time interval
between each conversion cycle is defined by:
2^(SampDiv) * 2^(SSLPdiv) * 0.5 sec
SHELF
POR
sPOR
Note that if the time taken to complete an A/D
conversion cycle is more than the defined
interval, the time-overlapped pending
conversion cycle(s) will be skipped until the
previous conversion cycle is complete.
Shelf-Sleep Mode enable: Setting this bit to ‘1’
will prepare the device for Shelf-Sleep mode. The
Shelf- Sleep mode will not be entered until a
SMBus Stop condition occurs, when both SDA
and SCL pins go low.
Power-on Reset Flag: This bit will read a ‘1’
when a Power-on Reset has occurred. Writing a
‘0’ to this bit will clear the POR flag.
Soft Reset: Writing a ‘1’ to this bit will cause the
device to re-initialize by reloading EEPROM
contents into all working registers. This function
has the same effect as the initial Power-on
Reset.
TRIP CONTROL REGISTER - TRIPctrl
(Address 76 Hex/118 Decimal)
7
6
5
4
3
2
1
0
lex lent VPex VPent GPADent Shent Rsvd Oflow
Iex
Note1
Exit from Sample-Sleep Mode on current: A ‘1’ in
this bit will enable an exit from Sample-Sleep
Mode upon the following condition: |current|
>I+Trip
Ient
Enter Sample-Sleep Mode on current: A ‘1’ in
this bit will enable entry to Sample-Sleep Mode
under the following condition: |current| <I-Trip
VPex
Note1
Exit from Sample-Sleep Mode on Pack voltage:
A ‘1’ in this bit will enable an exit from Sample-
Sleep Mode upon the following condition: VP >
VPtrip
VPent
Enter Sample-Sleep Mode on Pack voltage:
(Use VPent only if GPAD is not used and
grouned) A ‘1’ in this bit will enable entry to
Sample-Sleep Mode upon the following
condition: VP < VCtrip
GPADent
Enter Sample-Sleep Mode on GPAD voltage: A
‘1’ in this bit will enable entry to Sample-Sleep
Mode upon the following condition: GPAD <
VCtrip
Shent
Enter Shelf-Sleep Mode on Pack voltage: A ‘1’
in this bit will enable entry to Shelf-Sleep mode
upon the following condition: VP < SStrip
Rsvd
Reserved bit.
Oflow
ADC Overflow flag: This bit is set when the ADC
input voltage is beyond the designed voltage
range of the ADC. This bit will remain set until a
‘0’ is written to it.
Note1: The exit conditions are verifyed by design but not
tested in production.
20
FN9074.0
October 25, 2005