ISL6295 Datasheet, PDF (12/25 Pages) Intersil Corporation – Low Voltage Fuel Gauge

ISL6295
Figures 3 through 6 detail how data transfer is accomplished
on the SMBus. Depending upon the state of the R/W bit, two
types of data transfer are possible:
1. Data transfer from a master transmitter to a slave
receiver: The first byte transmitted by the master is the
slave address. Next follows a number of data bytes. The
slave returns an Acknowledge bit after each received
byte.
2. Data transfer from a slave transmitter to a master
receiver: The first byte (slave address) is transmitted by
the master. The slave then returns an Acknowledge bit.
Next follows a number of data bytes transmitted by the
slave to the master. The master returns an Acknowledge
bit after all received bytes other than the last byte. At the
end of the last received byte, a 'Not Acknowledge' is
returned.
The master device generates all of the serial clock pulses
and the START and STOP conditions. A transfer is ended
with a STOP condition or with a Repeated START condition.
Since a Repeated START condition is also the beginning of
the next serial transfer, the bus will not be released.
The ISL6295 may operate in the following two modes:
1. Slave receiver mode: Serial data and clock are received
through SDA and SCL. After each byte is received, an
acknowledge bit is transmitted. START and STOP
conditions are recognized as the beginning and end of a
serial transfer. Address recognition is performed by
hardware after reception of the slave address and
direction bit.
2. Slave transmitter mode: The first byte is received and
handled as in the Slave Receiver mode. However, in this
mode, the direction bit will indicate that the transfer
direction is reversed. Serial data is transmitted on SDA by
the ISL6295 while the serial clock is input on SCL. START
and STOP conditions are recognized as the beginning
and end of a serial transfer.
Ā
7
10
S
SMBus Address
0_A
76
43210
BT
X
Bank AH A
7
0
Address Low
A
7
0
# of Bytes (only if BT = 1) ^A
(Additional data bytes if BT =1)
7
0
Last write data byte
A
7
Legend:
S
P
RS
A
A
BT
Bank
PEC
AH
Add l
0
PEC (optional)
A/A
P
Master controls SDA
ISL6295 controls SDA
-Start
- Stop
- Repeated start
- Acknowdedge
- Negative Acknowledge (terminates transaction)
- Block mode indicator bit
- Controls selection of bank:
00: EEPROM
10: Reserved
01: RAM / Registers
- Packet Error Code
11: Reserved
- High order address bits (2)
FIGURE 7. ISL6295 SMBus WRITE TRANSACTION
12
FN9074.0
October 25, 2005