X9523_06 Datasheet, PDF (2/28 Pages) Intersil Corporation – Laser Diode Control for Fiber Optic Modules

X9523
Ordering Information
PART
NUMBER
PART
TEMP RANGE
MARKING
(°C)
PACKAGE
X9523V20I-A X9523VIA
-40 to +85 20 Ld TSSOP
X9523V20I-B X9523VIB
-40 to +85 20 Ld TSSOP
X9523V20IZ-A X9523VZIA
(Note)
-40 to +85 20 Ld TSSOP
(Pb-free)
X9523V20IZ-B X9523VZIB
(Note)
-40 to +85 20 Ld TSSOP
(Pb-free)
*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
DETAILED DEVICE DESCRIPTION
The X9523 combines two Intersil Digitally Controlled
Potentiometer (DCP) devices, V1/Vcc power-on reset
control, V1/Vcc low voltage reset control, and two sup-
plementary voltage monitors in one package. These
functions are suited to the control, support, and monitor-
ing of various system parameters in fiber optic modules.
The combination of the X9523 functionality lowers sys-
tem cost, increases reliability, and reduces board space
requirements.
Two high resolution DCPs allow for the “set-and-forget”
adjustment of Laser Driver IC parameters such as Laser
Diode Bias and Modulation Currents.
Applying voltage to V_CC activates the Power-on Reset
circuit which allows the V1RO output to go HIGH, until
the supply the supply voltage stabilizes for a period of
time (selectable via software). The V1RO output then
goes LOW. The Low Voltage Reset circuitry allows the
V1RO output to go HIGH when V_CC falls below the mini-
mum V_CC trip point. V1RO remains HIGH until V_CC
returns to proper operating level. A Manual Reset (MR)
input allows the user to externally trigger the V1RO out-
put (HIGH).
PIN CONFIGURATION
R_H2
R_W2
R_L2
V3
V3RO
MR
WP
SCL
SDA
V_SS
20 Pin TSSOP
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
V1 / Vcc
V1RO
V2RO
V2
NC
NC
NC
R_H1
R_W1
R_L1
NOT TO SCALE
Two supplementary Voltage Monitor circuits continuously
compare their inputs to individual trip voltages. If an input
voltage exceeds it’s associated trip level, a hardware out-
put (V3RO, V2RO) are allowed to go HIGH. If the input
voltage becomes lower than it’s associated trip level, the
corresponding output is driven LOW. A corresponding
binary representation of the two monitor circuit outputs
(V2RO and V3RO) are also stored in latched, volatile
(CONSTAT) register bits. The status of these two moni-
tor outputs can be read out via the 2-wire serial port.
Intersil’s unique circuits allow for all internal trip volt-
ages to be individually programmed with high accu-
racy. This gives the designer great flexibility in
changing system parameters, either at the time of
manufacture, or in the field.
The device features a 2-Wire interface and software
protocol allowing operation on an I²C™ compatible
serial bus.
2
FN8209.1
January 3, 2006