X5001 Datasheet, PDF (2/18 Pages) Xicor Inc. – CPU Supervisor

PIN CONFIGURATION
RESET
V_CC
CS/WDI
SO
8-Lead TSSOP
1
8
2 _X5001 7
3
6
4
5
X5001
SCK
SI
V_SS
V_PE
8-Lead SOIC/PDIP
CS/WDI
SO
V_PE
V_SS
1
8
2 _X5001 7
3
6
4
5
V_CC
RESET
SCK
SI
PIN DESCRIPTION
Pin
(SOIC/PDIP)
1
2
5
6
3
4
8
7
Pin
TSSOP
1
2
8
9
6
7
14
13
3-5,10-12
Name
CS/WDI
SO
SI
SCK
V_PE
V_SS
V_CC
RESET
NC
Function
Chip Select Input. CS HIGH, deselects the device and the SO output pin is at
a high impedance state. Unless a nonvolatile write cycle is underway, the device
will be in the standby power mode. CS LOW enables the device, placing it in the
active power mode. Prior to the start of any operation after power-up, a HIGH to
LOW transition on CS is required.
Watchdog Input. A HIGH to LOW transition on the WDI pin restarts the Watch-
dog timer. The absence of a HIGH to LOW transition within the watchdog time
out period results in RESET/RESET going active.
Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data
out on this pin. The falling edge of the serial clock (SCK) clocks the data out.
Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and
memory data on this pin. The rising edge of the serial clock (SCK) latches the
input data. Send all opcodes (Table 1), addresses and data MSB first.
Serial Clock. The Serial Clock controls the serial bus timing for data input and
output. The rising edge of SCK latches in the opcode, address, or watchdog bits
present on the SI pin. The falling edge of SCK changes the data output on the
SO pin.
V_TRIP Program Enable. When V_PE is LOW, the V_TRIP point is fixed at the last
valid programmed level. To readjust the V_TRIP level, requires that the V_PE pin be
pulled to a high voltage (15-18V).
Ground
Supply Voltage
Reset Output. RESET is an active LOW, open drain output which goes active
whenever V_CC falls below the minimum V_CC sense level. It will remain active un-
til V_CC rises above the minimum V_CC sense level for 200ms. RESET goes active
if the watchdog timer is enabled and CS/WDI remains either HIGH or LOW long-
er than the selectable watchdog time out period. A falling edge of CS/WDI will
reset the watchdog timer. RESET goes active on power-up at 1V and remains
active for 200ms after the power supply stabilizes.
No internal connections
2
FN8125.0
April 6, 2005