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| X5001 Datasheet, PDF (13/18 Pages) Xicor Inc. – CPU Supervisor | |||
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X5001
Figure 13. CS vs. RESET Timing
CS
RESET
tCST
tWDO
tRST
RESET Output Timing
Symbol
tWDO
tCST
tRST
Parameter
Watchdog timeout period,
WD1 = 1, WD0 = 0
WD1 = 0, WD0 = 1
WD1 = 0, WD0 = 0
CS pulse width to reset the watchdog
Reset Timeout
VTRIP Programming Timing Diagram
VCC
(VTRIP)
VTRIP
VP
VPE
CS
tVPS
tPCS
SCK
tWDO
tRST
Min.
100
450
1
400
100
Typ.
200
600
1.4
200
Max.
300
800
2
300
tTSU
tTHD
tVPH
tVPO
tRP
SI
03h
0001h
02h
0001h or
0003h
Unit
ms
ms
sec
ns
ms
13
FN8125.0
April 6, 2005
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