ISL78420 Datasheet, PDF (2/16 Pages) Intersil Corporation – 100V, 2A Peak, Half-Bridge Driver with Tri-Level PWM Input and Adjustable Dead-Time

Block Diagram
VDD
5V
PWM
EN
RDT
-
+
-
+
5V
210k
ISL78420
HB
UNDER
LEVEL
HO
VOLTAGE
SHIFT
HS
DELAY
DELAY
UNDER
VOLTAGE
LO
VSS
ISL78420
Pin Configurations
ISL78420ARTAZ
(10 LD 4X4 TDFN)
TOP VIEW
VDD 1
HB 2
HO 3
HS 4
NC 5
EPAD
10 LO
9 VSS
8 PWM
7 EN
6 RDT
ISL78420ARTBZ
(9 LD 4X4 TDFN)
TOP VIEW
VDD 1
HB 3
HO 4
HS 5
EPAD
10 LO
9 VSS
8 PWM
7 EN
6 RDT
EPAD
Pin Descriptions
10 9
LD LD SYMBOL
DESCRIPTION
11
VDD Positive supply voltage for lower gate driver.
Decouple this pin to ground with a 4.7µF or larger
ceramic capacitor to VSS
23
HB High-side bootstrap supply voltage referenced to
HS. Connect bootstrap capacitor to this pin and HS.
3 4 HO High-side output connected to gate of high-side FET.
45
HS High-side source connect to source of high-side FET.
Connect bootstrap capacitor to this pin and HB.
88
PWM
PWM input. For PWM = 5V, HO = 1, LO = 0. For
PWM = 0V, HO = 0, LO = 1. For PWM = 2.5V,
HO = LO = 0.
7 7 EN Output enable, when low, HO = LO = 0
9 9 VSS Negative voltage supply, Connected to ground.
10 10 LO Low-side output. Connect to gate of low-side FET.
5-
NC No Connect. This pin is isolated from all other pins.
May optionally be connected to VSS. Note that on
the 9 Ld package, there is no pin present at the
location normally occupied by pin 2.
66
RDT A resistor connected between this pin and VSS adds
dead time by adding delay time to the falling and
rising edges of the PWM input.
- - EPAD The epad is electrically isolated. It is recommended
that the epad be connected to the VSS plane for
heat removal.
2
FN8296.1
September 24, 2012