ISL78420 Datasheet, PDF (11/16 Pages) Intersil Corporation – 100V, 2A Peak, Half-Bridge Driver with Tri-Level PWM Input and Adjustable Dead-Time

ISL78420
8V TO 15V
VDD
HB
PWM*
PWM
CONTROLLER
PWM
EN
RDT
HI
HO
DRIVER
HS
LO
LO
DRIVER
VSS
ISL78420
100V MAX
FIGURE 19. TYPICAL ACTIVE CLAMP FORWARD APPLICATION
Typical Application Circuit
Figure 19 is an example of how the ISL78420 can be configured
for an active clamp forward power supply application. Note that
the PWM signal from the controller must be inverted for this
active clamp forward topology.
Depending on the application, the switching speed of the bridge
FETs can be reduced by adding series connected resistors
between the xHO outputs and the FET gates. Gate-Source
resistors are recommended on the low-side FETs to prevent
unexpected turn-on of the bridge should the bridge voltage be
applied before VDD. Gate-source resistors on the high-side FETs
are not usually required if low-side gate-source resistors are
used. If relatively low value gate-source resistors are used on the
high-side FETs, be aware that a larger value for the boot capacitor
may be required.
Transients on HS Node
An important operating condition that is frequently overlooked by
designers is the negative transient on the xHS pins that occurs
when the high-side bridge FET turns off. The Absolute Maximum
transient allowed on the xHS pin is -6V but it is wise to minimize
the amplitude to lower levels. This transient is the result of the
parasitic inductance of the low-side drain-source conductor on
the PCB. Even the parasitic inductance of the low-side FET
contributes to this transient.
When the high-side bridge FET turns off (see Figure 20), because
of the inductive characteristics the load, the current that was
flowing in the high-side FET (blue) must rapidly commutate to
flow through the low-side FET (red). The amplitude of the
negative transient impressed on the xHS node is (di/dt x L) where
L is the total parasitic inductance of the low-side FET
drain-source path and di/dt is the rate at which the high-side FET
is turned off. With the increasing power levels of power supplies
and motors, clamping this transient become more and more
significant for the proper operation of the ISL78420.
HB
HO
IN D U C T IV E
LOAD
HS
-
+
LO
-
VSS
+
FIGURE 20. PARASITIC INDUCTANCE CAUSES TRANSIENTS ON HS
NODE
There are several ways of reducing the amplitude of this
transient. If the bridge FETs are turned off more slowly to reduce
di/dt, the amplitude will be reduced but at the expense of more
switching losses in the FETs. Careful PCB design will also reduce
the value of the parasitic inductance. However, these two
solutions by themselves may not be sufficient. Figure 20
illustrates a simple method for clamping the negative transient.
A fast PN junction, 1A diode is connected between xHS and VSS
as shown. It is important that this diode be placed as close as
possible to the xHS and VSS pins to minimize the parasitic
inductance of this current path. Because this clamping diode is
essentially in parallel with the body diode of the low-side FET, a
small value resistor is necessary to limit current when the body
diode of the low-side bridge FET is conducting during the dead
time. The resistor in series with HS, can be used instead of the
gate resistor of the high-side FET.
Please note that a similar transient with a positive polarity occurs
when the low-side FET turns off. This is less frequently a problem
because xHS node is floating up toward the bridge bias voltage.
The Absolute Max voltage rating for the xHS node does need to
be observed when the positive transient occurs.
11
FN8296.1
September 24, 2012