ISL78200 Datasheet, PDF (2/19 Pages) Intersil Corporation – 2.5A Regulator with Integrated High-Side MOSFET for Synchronous Buck or Boost Buck Converter

Pin Configuration
ISL78200
ISL78200
(20 LD HTSSOP)
TOP VIEW
PGND 1
BOOT 2
VIN 3
VIN 4
SGND 5
VCC 6
AUXVCC 7
EN 8
FS 9
SS 10
21
PAD
20 LGATE
19 SYNC
18 EXT_BOOST
17 PHASE
16 PHASE
15 PGOOD
14 MODE
13 ILIMIT
12 COMP
11 FB
Functional Pin Description
PIN NAME
PGND
BOOT
VIN
SGND
VCC
AUXVCC
EN
FS
SS
FB
COMP
ILIMIT
MODE
PGOOD
PIN #
1
2
3, 4
5
6
7
8
9
10
11
12
13
14
15
DESCRIPTION
This pin is used as the ground connection of the power flow including driver.
This pin provides bias voltage to the high-side MOSFET driver. A bootstrap circuit is used to create a voltage suitable to drive
the internal N-channel MOSFET. The boot charge circuitries are integrated inside of the IC. No external boot diode is needed. A
1µF ceramic capacitor is recommended to be used between BOOT and PHASE pin.
Connect the input rail to these pins that are connected to the drain of the integrated high-side MOSFET, as well as the source
for the internal linear regulator that provides the bias of the IC. Range: 3V to 40V.
With the part switching, the operating input voltage applied to the VIN pins must be under 40V. This recommendation allows
for short voltage ringing spikes (within a couple of ns time range) due to switching while not exceeding Absolute Maximum
Ratings.
This pin provides the return path for the control and monitor portions of the IC.
This pin is the output of the internal linear regulator that supplies the bias for the IC including the driver. A minimum 4.7µF
decoupling ceramic capacitor is recommended between VCC to ground.
This pin is the input of the auxiliary internal linear regulator which can be supplied by the regulator output after power-up. With
such a configuration, the power dissipation inside the IC is reduced. The input range for this LDO is 3V to 20V.
In boost mode operation, this pin works as boost output overvoltage detection pin. It detects the boost output through a resistor
divider. When voltage on this pin is above 0.8V, the boost PWM is disabled; and when voltage on this pin is below 0.8V minus
the hysteresis, the boost PWM is enabled. Range: 3V to 20V.
The controller is enabled when this pin is pulled HIGH. The IC is disabled when this pin is pulled LOW. Range: 0V to 5.5V.
To connect this pin to VCC, or GND, or left open will force the IC to have 500kHz switching frequency. The oscillator switching
frequency can also be programmed by adjusting the resistor from this pin to GND.
Connect a capacitor from this pin to ground. This capacitor, along with an internal 5µA current source, sets the soft-start
interval of the converter. Also this pin can be used to track a ramp on this pin.
This pin is the inverting input of the voltage feedback error amplifier. With a properly selected resistor divider connected from
V_OUT to FB, the output voltage can be set to any voltage between the input rail (reduced by maximum duty cycle and voltage
drop) and the 0.8V reference. Loop compensation is achieved by connecting an RC network across COMP and FB. The FB pin
is also monitored for overvoltage events.
Output of the voltage feedback error amplifier.
Programmable current limit pin. With this pin connected to VCC pin, or to GND, or left open, the current limit threshold is set
to default 3.6A; the current limit threshold can be programmed with a resistor from this pin to GND.
Mode selection pin. Pull this pin to GND for forced PWM mode; to have it floating or connected to VCC will enable PFM mode
when the peak inductor current is below the default threshold of 700mA. The current boundary threshold between PFM and
PWM can also be programmed with a resistor at this pin to ground. For more details on PFM Mode Operation refer to the
“Functional Description” on page 13.
PGOOD is an open drain output that will be pulled low immediately under the events when the output is out of regulation (OV
or UV) or EN pin pulled low. PGOOD is equipped with a fixed delay of 1000 cycles upon output power-up (V_O > 90%).
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FN7641.0
September 22, 2011