ISL6144_07 Datasheet, PDF (2/29 Pages) Intersil Corporation – High Voltage ORing MOSFET Controller

Pinouts
ISL6144
(16 LD TSSOP)
TOP VIEW
GATE 1
VIN 2
HVREF 3
NC ⁴
NC ⁵
NC ⁶
NC ⁷
GND ⁸
16 VOUT
15 COMP
14 VSET
13 NC
12 NC
11 NC
10 NC
9 FAULT
ISL6144
ISL6144
(20 LD 5x5 QFN)
TOP VIEW
20 19 18 17 16
VIN 1
HVREF 2
NC 3
NC 4
NC 5
15 VOUT
14 COMP
13 VSET
12 NC
11 NC
6 7 8 9 10
Pin Descriptions
TSSOP QFN
PIN # PIN #
SYMBOL
FUNCTION
DESCRIPTION
1
19
GATE External FET Gate Drive
Allows active control of external N-Channel FET gate to perform ORing
function.
2
1
VIN Power Supply Connection
Chip bias input. Also provides a sensing node for external FET control.
3
2
HVREF Chip High Voltage Reference
Low side of floating high voltage reference for all of the HV chip circuitry.
8
7
GND Chip Ground Reference
Chip ground reference point.
9
9
FAULT Fault Output
Provides an open drain active low output as an indication that a fault has
occurred: GATE is OFF (GATE < V_IN + 0.37V) or other types of faults
resulting in V_IN - V_OUT > 0.41V.
14
13
VSET Low Side Connection for Trip Level Resistor connected to COMP provides adjustable “Vd-Vs” trip level along
with pin COMP.
15
14
COMP High Side Connection for HS
Resistor connected to V_OUT provides sense point for the adjustable Vd-Vs
Comparator Trip Level
trip level along with pin VSET.
16
15
VOUT Chip Bias and Load Connection Provides the second sensing node for external FET control and chip output
bias.
4-7,
3-6, 8,
NC No Connection
10-13 10-12,
16-18, 20
2
FN9131.3
February 15, 2007