ICL7126_14 Datasheet, PDF (2/15 Pages) Intersil Corporation – 3 1/2 Digit, Low Power, Single Chip A/D Converter

ICL7126
Absolute Maximum Ratings
Supply Voltage V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15V
Analog Input Voltage (Either Input) (Note 1) . . . . . . . . . . . . .V+ to V-
Reference Input Voltage (Either Input) . . . . . . . . . . . . . . . . .V+ to V-
Clock Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TEST to V+
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0^oC to 70^oC
Thermal Information
Thermal Resistance (Typical, Note 2)
θ_JA (^oC/W)
PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
50
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150^oC
Maximum Storage Temperature Range . . . . . . . . . . -65^oC to 150^oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300^oC
NOTE: Pb-free PDIPs can be used for through hole wave solder
processing only. They are not intended for use in Reflow solder
processing applications.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Input voltages may exceed the supply voltages provided the input current is limited to ±100µA.
2. θ_JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications T_A = 25^oC, V_REF = 100mV, f_CLOCK = 48kHz (Notes 1, 3)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNITS
SYSTEM PERFORMANCE
Zero Input Reading
V_IN = 0.0V, Full Scale = 200mV
-000.0 ±000.0 +000.0 Digital
Reading
Ratiometric Reading
V_lN = V_REF, V_REF = 100mV
999 999/100 1000 Digital
0
Reading
Rollover Error
-V_IN = +V_lN ≅ 200mV
Difference in Reading for Equal Positive and Negative
Inputs Near Full Scale
-
±0.2
±1 Counts
Linearity
Full Scale = 200mV or Full Scale = 2V Maximum Deviation
-
from Best Straight Line Fit (Note 5)
±0.2
±1 Counts
Common Mode Rejection Ratio
Noise
V_CM = ±1V, V_IN = 0V, Full Scale = 200mV (Note 5)
-
50
-
µV/V
V_IN = 0V, Full Scale = 200mV
-
15
-
µV
(Peak-To-Peak Value Not Exceeded 95% of Time) (Note 5)
Leakage Current Input
Zero Reading Drift
Scale Factor Temperature Coefficient
V_lN = 0V (Note 5)
V_lN = 0V, 0^oC To 70^oC (Note 5)
(VE^INxt.=R1e9f9. ^m0pVp,m0/o×^CoC^To)
70^oC,
(Note
5)
-
1
10
pA
-
0.2
1
µV/^oC
-
1
5
ppm/^oC
V+ Supply Current
COMMON Pin Analog Common Voltage
V_IN = 0V (Does Not Include COMMON Current)
25kΩ Between Common and Positive Supply
(With Respect to + Supply)
Temperature Coefficient of Analog Common 25kΩ Between Common and Positive Supply
(With Respect to + Supply) (Note 5)
-
70
100
µA
2.4
3.0
3.2
V
-
80
-
ppm/^oC
Peak-To-Peak Segment Drive Voltage
Peak-To-Peak Backplane Drive Voltage
V+ = to V- = 9V (Note 4)
4
5.5
6
V
Power Dissipation Capacitance
vs Clock Frequency
-
40
-
pF
NOTES:
3. Unless otherwise noted, specifications are tested using the circuit of Figure 1.
4. Back plane drive is in phase with segment drive for ‘off’ segment, 180 degrees out of phase for ‘on’ segment. Frequency is 20 times conversion
rate. Average DC component is less than 50mV.
5. Not tested, guaranteed by design.
2
FN3084.5