HIP7030A0 Datasheet, PDF (2/10 Pages) Intersil Corporation – J1850 8-Bit 68HC05 Microcontroller Emulator Version

HIP7030A0
Block Diagram
TCMP
35
34
TCAP
TIMER SYSTEM
49
PA0 ₄₈
PA1 ₄₇
PA2 ₄₆
PA3 ₄₅
PA4 ₄₄
PA5 ₄₃
PA6 ₄₂
PA7
19
PD0
18
PD1
17
PD2, V2
16
PD3, V3
15
PD4, VR
TCAP
PORT
A
REG
DATA
DIR
REG
PORT D
REG
+_-
PORT D PORT D
SFR
DIR
REG
REG
+_-
INTERNAL
PROCESSOR
CLOCK
OSCIN OSCOUT
24
23 ₅₀
OSCILLATOR
OSCB
AND ÷ 2
38
RESET
39
IRQ
ACCUMULATOR
8
A
INDEX
8
REGISTER
X
CONDITION CODE
5
REGISTER
CC
STACK
6
POINTER
S
PROGRAM
5 COUNTER HIGH PCH
PROGRAM
8 COUNTER LOW PCL
CPU
CONTROL
CPU
SYMBOL INT
VPW SYMBOL
ENCODER /
DECODER
AND
ARBITRATION
ALU
SPI
SYSTEM
37
VPWOUT
36 _VPWIN
32
SCK
26
25 ^MOSI
MISO
33
SS
13
DS
12
WE
9
CE
6
FS
5
RD
14
ALC
BUS
CONTROL
BUS DRIVE
176 x 8
STATIC RAM
INTERNAL PROCESSOR CLOCK
WATCHDOG AND
SLOW CLOCK DETECT
ADDRESS DRIVE
V_SS 22
V_DD 7
9-41