CD4033BMS Datasheet, PDF (2/11 Pages) Intersil Corporation – CMOS Decade Counter/Divider

CD4033BMS
The CD4033BMS has provisions for automatic blanking of
the non-significant zeros in a multi-digit decimal number
which results in an easily readable display consistent with
normal writing practice. For example, the number 0050.0700
in an eight digit display would be displayed as 50.07. Zero
suppression on the integer side is obtained by connecting
the RBI terminal of the CD4033BMS associated with the
most significant digit in the display to a low-level voltage and
connecting the RBO terminal of that stage to the RBI termi-
nal of the CD4033BMS in the next-lower significant position
in the display. This procedure is continued for each succeed-
ing CD4033BMS on the interger side of the display.
On the fraction side of the display the RBI of the
CD4033BMS associated with the least significant bit is con-
nected to a low-level voltage and the RBO of that
CD4033BMS is connected to the RBI terminal of the
CD4033BMS in the next more-significant-bit position. Again,
this procedure is continued for all CD4033BMS’s on the frac-
tion side of the display.
In a purely fractional number the zero immediately preceding
the decimal point can be displayed by connecting the RBI of
that stage to a high level voltage (instead of to the RBO of
the next more-significant-stage). For example: optional zero
→ 0.7346. Likewise, the zero in a number such as 763.0 can
be displayed by connecting the RBI of the CD4033BMS
associated with it to a high-level voltage.
Ripple blanking of non-significant zeros provides an appre-
ciable savings in display power.
The CD4033BMS has a LAMP TEST input which, when con-
nected to a high-level voltage, overrides normal decoder
operation and enables a check to be made on possible dis-
play malfunctions by putting the seven outputs in the high
state.
The CD4033BMS are supplied in these 16 lead outline pack-
ages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
H4W
H2R
H6W
Logic Diagram
*LAMP TEST
14
DQ
CL
CL _Q
15*
R
DQ
CL
CL _Q
R
DQ
CL
CL _Q
R
DQ
CL
CL _Q
R
DQ
CL
CL _Q
R
RESET
COUT
(CLOCK ÷ 10)
5
10
a
12
b
1
*CLOCK
*CLOCK
CL
INHIBIT ²
3
*RBI
16
VDD
8
GND
*ALL INPUTS PROTECTED
BY CMOS INPUT
PROTECTION NETWORK
VDD
VSS
FIGURE 1. CD4033BMS
a
fg
e
d
b
SEGMENT
DESIGNATIONS
c
13
c
9
d
11
e
6
f
7
g
4
RBO
7-827