X40020_06 Datasheet, PDF (19/24 Pages) Intersil Corporation – Dual Voltage Monitor with Integrated CPU Supervisor and System Battery Switch

WP Pin Timing
SCL
START
SDA IN
WP
t_SU:WP
X40020, 40021
Clk 1
Slave Address Byte
Clk 9
t_HD:WP
Write Cycle Timing
SCL
SDA
8^th Bit of Last Byte
ACK
t_WC
Stop
Condition
Start
Condition
Nonvolatile Write Cycle Timing
Symbol
t_WC(1)
Parameter
Write Cycle Time
Min.
Typ.⁽¹⁾
5
Max.
10
Unit
ms
Note: (1) t_WC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is
the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
Power Fail Timings
V_TRIPX
V_CC or
V2MON
LOWLINE or
t_R
V2FAIL
t_RPDL
t_RPDX
V_RVALID
t_RPDL
t_RPDX
t_RPDL
t_RPDX
t_F
X = 1, 2
19
FN8112.1
May 17, 2006