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X40020_06 Datasheet, PDF (1/24 Pages) Intersil Corporation – Dual Voltage Monitor with Integrated CPU Supervisor and System Battery Switch
®
Data Sheet
X40020, X40021
May 17, 2006
FN8112.1
Dual Voltage Monitor with Integrated CPU
Supervisor and System Battery Switch
FEATURES
• Dual voltage detection and reset assertion
—Three standard reset threshold settings
(4.6V/2.9V, 4.6V/2.6V, 2.9V/1.6V)
—VTRIP2 programmable down to 0.9V
—Adjust low voltage reset threshold voltages
using special programming sequence
—Reset signal valid to VCC = 1V
—Monitor two voltages or detect power fail
• Battery switch backup
• VOUT: 5mA to 50mA from VCC; 250µA from VBATT
• Fault detection register
• Selectable power-on reset timeout
(0.05s, 0.2s, 0.4s, 0.8s)
• Selectable watchdog timer interval
(25ms, 200ms, 1.4s, off)
• Debounced manual reset input
• Low power CMOS
—25µA typical standby current, watchdog on
—6µA typical standby current, watchdog off
—1µA battery current in backup mode
• 400kHz 2-wire interface
• 2.7V to 5.5V power supply operation
• Available packages
—14-lead SOIC, TSSOP
• Monitor voltages: 5V to 1.6V
• Memory security
• Pb-free plus anneal available (RoHS compliant)
APPLICATIONS
• Communications equipment
—Routers, hubs, switches
—Disk arrays
• Industrial systems
—Process control
—Intelligent instrumentation
• Computer systems
—Desktop computers
—Network servers
X40020, X40021
Standard VTRIP1 Level Standard VTRIP2, Level
4.6V (±1%)
2.9V(±1.7%)
4.6V (±1%)
2.6V (±2%)
2.9V(±1.7%)
1.6V (±3%)
See “Ordering Information” for more details
For Custom Settings, call Intersil.
Suffix
-A
-B
-C
DESCRIPTION
The X40020 combines power-on reset control, watch-
dog timer, supply voltage supervision, and secondary
supervision, and manual reset, in one package. This
combination lowers system cost, reduces board space
requirements, and increases reliability.
Applying voltage to VCC activates the power-on reset
circuit which holds RESET/RESET active for a period of
time. This allows the power supply and system oscilla-
tor to stabilize before the processor can execute code.
BLOCK DIAGRAM
V2MON
SDA
WP
SCL
VCC
(V1MON)
BATT-ON
VOUT
VBATT
Data
Register
Command
Decode Test
& Control
Logic
System
Battery
Switch
V2 Monitor
Logic
VOUT
+
VTRIP2
-
Fault Detection
Register
Status
Register
Watchdog
and
Reset Logic
VOUT
VCCLMogoicnitor
VOUT
+
VTRIP1
-
Power-on,
Manual Reset
Low Voltage
Reset
Generation
V2FAIL
WDO
MR
RESET
X40020
RESET
X40021
LOWLINE
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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