ISL6253 Datasheet, PDF (19/22 Pages) Intersil Corporation – Highly Integrated Battery Charger for Notebook Computers

ISL6253
Figure 20 shows the type II compensator and its transfer
function is expressed as follows:
A_v(S)
=
-^vˆ---c_vˆ---^oF---^m-_B----^p-
=
C^-----₁^--g--+--m---C^-----₂^-
1 + ----^S-----
----------------^ω----^c---^z------
S


1
+
ω^----S-_c^---_p^{-}
(EQ. 26)
where
ω_cz
=
-------¹------- ,
R₁C₁
ω_cp
=
--^C----¹-----+----^C-----²--
R₁C₁C₂
Compensator design goal:
• High DC gain
•
Loop bandwidth f_c:


1_--
5
–
3^--1--0^{--}
f_s
• Gain margin: >10dB
• Phase margin: 40°
The compensator design procedure is as follows:
1. Put compensator zero at
ω_cz
=
(1 – 3)
-------¹-------
R_oC_o
2. Put one compensator pole at zero frequency to achieve
high DC gain, and put another compensator pole at either
esr zero frequency or half switching frequency, whichever
is lower.
The loop gain T_v(S) at cross over frequency of f_c has unity
gain. Therefore, the compensator resistance R₁ is
determined by:
R₁
=
2_----π_----f_--c---V_----o----C_----o----R_----T--
g_mV_FB
(EQ. 27)
where g_m is the trans-conductance of the voltage error
amplifier. Compensator capacitor C1 is then given by:
C₁
=
--------¹---------,
R₁ω_cz
C₂
=
-₂---_π----_R-----₁---_C--^C---₁--¹-_f--_e---_s---_r---–-----₁--
(EQ. 28)
Example: V_in = 20V, V_o = 16.8V, I_o = 4A, f_s = 300kHz,
C_o = 22µF/10mΩ, L = 15µH, g_m = 250µs, R_T = 0.15Ω
(R_cs = 25mΩ, A_c = 6), V_FB = 2.1V, V_PWM = V_IN/11,
f_c = 15kHz, then compensator resistance R₁ = 10kΩ.
Put the compensator zero at 1.7kHz, and put the
compensator pole at esr zero which is 725kHz. The
compensator capacitors are:
C₁ = 10nF, C₂ = 22pF
Such small C₂ may not be necessary since it does not affect
the phase and gain at such high frequency.
PCB Layout Considerations
Power and Signal Layer Placement on the PCB
As a general rule, power layers should be close together,
either on the top or bottom of the board, with signal layers on
the opposite side of the board. For example, layer
arrangement on a 4 layer board is shown below:
Layer 1: Small signal external components
Layer 2: Signal Ground
Layer 3: Power Ground
Layer 4: Bottom Layer: Power MOSFET, Inductors and
other Power traces
Separate the power voltage and current flowing path from
the control and logic level signal path. The controller IC will
stay on the signal layer, which is isolated by the signal
ground to the power signal traces.
Component Placement
The power MOSFET should be close to the IC so that the
gate drive signal, the LGATE, UGATE, PHASE, and BOOT
traces can be short.
Place the components in such a way that the area under the
IC has fewer noise traces with high dv/dt and di/dt, such as
gate signals and phase node signals.
SIGNAL GROUND AND POWER GROUND CONNECTION
At minimum, a reasonably large area of copper, which will
shield other noise couplings through the IC, should be used
as signal ground beneath the IC. The best tie-point between
the signal ground and the power ground is at the negative
side of the output capacitor on each side, where there is little
noise; a noisy trace beneath the IC is not recommended.
GND AND VDD PIN
At least one high quality ceramic decoupling cap should be
used to cross the GND and VDD pins. The decoupling cap
can be put close to the IC.
LGATE PIN
This is the gate drive signal for the bottom MOSFET of the
buck converter. The signal going through this trace has both
high dv/dt and high di/dt, and the peak charging and
discharging current is very high. These two traces should be
short, wide, and away from other traces. There should be no
other traces in parallel with these traces on any layer.
PGND PIN
The PGND pin should be laid out to the negative side of the
relevant output cap with separate traces. The negative side
of the output capacitor must be close to the source node of
the bottom MOSFET.
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