ISL6253 Datasheet, PDF (16/22 Pages) Intersil Corporation – Highly Integrated Battery Charger for Notebook Computers

ISL6253
For V_IN,MAX = 20V, V_BAT = 16.8V, I_BAT,MAX = 4A, and
f_s = 300kHz, the calculated inductance is 12.8µH. Choosing
the closest standard value gives L = 15µH. Ferrite cores are
often the best choice since they are optimized at 300kHz to
600kHz operation with low core loss. The core must be large
enough not to saturate at the peak inductor current I_Peak:
I_Peak=
I _{B A T ,M}
A
X
+
1_--
2
∆I_L
(EQ. 10)
Output Capacitor Selection
The output capacitor in parallel with the battery is used to
absorb the high frequency switching ripple current and
smooth the output voltage. The RMS value of the output
ripple current I_rms is given by:
I_RMS=
V_{-----I--N----,-M-----A----X--D(1 – D)}
12 L f_s
(EQ. 11)
where the duty cycle D is the ratio of the output voltage
(battery voltage) over the input voltage for continuous
conduction mode, which is typical operation for a battery
charger. During the battery charge period, the output voltage
varies from its initial battery voltage to the rated battery
voltage; therefore, the duty cycle change can be in the range
of between 0.375 and 0.63 for the minimum battery voltage
of 7.5V (2.5V/Cell) and the maximum battery voltage of
12.8V. The maximum RMS value of the output ripple current
occurs at the duty cycle of 0.5 and is expressed as:
I_RMS=
V_{-----I--N----,-M-----A----X--}
4 12 Lf_s
(EQ. 12)
For V_IN,MAX = 20V, L = 15µH, and f_s = 300kHz, the
maximum RMS current is 0.32A. A typical 10µF or 22µF
ceramic capacitor is a good choice to absorb this current,
and also has very small size. The tantalum capacitor has a
known failure mechanism when subjected to high surge
current.
EMI considerations usually make it desirable to minimize
ripple current in the battery leads. Beads may be added in
series with the battery pack to increase the battery
impedance at 300kHz switching frequency. Switching ripple
current splits itself between the battery and the output
capacitor, depending on the ESR of the output capacitor and
the battery impedance. If the ESR of the output capacitor is
20mΩ and the battery impedance is raised to 2Ω with a
bead, then only 1% of the ripple current will flow in the
battery.
MOSFET Selection
The notebook battery charger synchronous buck converter
has input voltage from the AC adapter output. The maximum
AC adapter output voltage does not exceed 25V; therefore, a
30V logic MOSFET should be used.
The high side MOSFET must be able to dissipate the
conduction losses plus the switching losses. For the battery
charger application, the input voltage of the synchronous
buck converter is equal to the AC adapter output voltage,
which is relatively constant. The maximum efficiency is
achieved by selecting a high side MOSFET that has the
conduction losses equal to the switching losses. Ensure that
the ISL6253 LGATE gate driver can supply sufficient gate
current to prevent it from conduction, which is due to the
injected current into the drain-to-source parasitic capacitor
(Miller capacitor C_gd), and caused by the voltage rising rate
at the phase node at the moment of the high-side MOSFET
turning on; otherwise, cross-conduction problems may
occur. Reasonably slowing the turn-on speed of the high-
side MOSFET, by connecting a resistor between the BOOT
pin and gate drive supply source, and the high sink current
capability of the low-side MOSFET gate driver, helps reduce
the possibility of cross-conduction.
For the high-side MOSFET, the worst-case conduction
losses occur at the minimum input voltage:
P_{Q 1 ,C o n d u c t i o n} =
V_{-----O----U----T--}
V_IN
I_B2
A
T
R_DSO
N
(EQ. 13)
The optimum efficiency occurs when the switching losses
equal the conduction losses. However, it is difficult to
calculate the switching losses in the high-side MOSFET
since it must allow for difficult-to-quantify factors that
influence the turn-on and turn-off times. These factors
include: the MOSFET internal gate resistance, gate charge,
threshold voltage, stray inductance, and pull-up and pull-
down resistance of the gate driver. The following switching
loss calculation provides a rough estimate:
(EQ. 14)
P_{Q 1 ,S w i t c h i n g}
=
1_--
2
V_I
N
I_L
V
f_s
-------^Q-----^g---^d-------- +
I _{g ,s o u r c e}
1_--
2
V_IN
I_L
P
f_s
---^Q-----^g----^d----
I_{g , sin k}
+
Q_r
r
V_I
N
f_s
where Q_gd is drain-to-gate charge; Q_rr is total reverse
recovery charge of the body-diode in low side MOSFET; I_LV
is inductor valley current; I_LP is Inductor peak current; and
I_g,sink and I_g,_source are the peak gate-drive source/sink
current of Q1, respectively.
Achievement of low switching losses requires low drain-to-
gate charge, Q_gd. Generally, the lower the drain-to-gate
charge, the higher the on-resistance; therefore, there is a
trade-off between the on-resistance and drain-to-gate
charge. Good MOSFET selection is based on the Figure of
Merit (FOM), which is the product of the total gate charge
and on-resistance. Usually, the smaller the value of FOM,
the higher the efficiency for the same application.
For the low-side MOSFET, the worst-case power dissipation
occurs at minimum battery voltage and maximum input
voltage:
P_Q2
=

1

–
V_{----V-O---I-U-N---T--}
I_{B2 AT}R_DSON
(EQ. 15)
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