ISL59533 Datasheet, PDF (19/24 Pages) Intersil Corporation – 32x32 Video Crosspoint with Differential Inputs

Block Diagram
V_IN0
32 INPUTS
ISL59533
VS+ VOVERn OVERn
32
OVERLAY
INPUT
32
LOGIC
CONTROL
-
+
POWER-ON
SWITCH
MATRIX
32 OUTPUTS
-
V_IN31
+
REF
SDI
CLK
ENA
A_{V OUTPUT}
+1, +2 ENABLE
POWER-ON
SPI INTERFACE, REGISTER
SDO
General Description
The ISL59533 is a 32x32 integrated video crosspoint switch
matrix with differential input and output buffers and On-
Screen Display (OSD) insertion. This device operates from a
single +5V supply. Any output can be switched to any of the
32 input video signal sources and OSD information through
an internal, dedicated fast 2:1 mux located before the output
buffer. Also, any one input can be broadcast to all 32
outputs.
Each output X is defined as:
Voutx = Avx*(INx-INBx+REF)
Where Avx = 1, or Avx = 2. Note that all REF’s are common
between channels and must be externally well buffered
and/or bypassed.
The ISL59533 offers a -3dB signal bandwidth of 300MHz.
The differential gain and phase at 0.01% and 0.03°
respectively, along with 0.1dB flatness out to 35MHz. The
switch matrix configuration and output buffer gain are
programmed through an SPI/QSPI™-compatible, three-wire
serial interface. The ISL59533 interface is set up to facilitate
both fast updates and initialization. On power-up, all facilities
are initialized in the disabled state to avoid output conflicts
within the user system.
Digital Interface
The ISL59533 uses a simple 3-wire SPI compliant digital
interface to program the outputs. The ISL59533 can support
the clock rate up to 5MHz.
Serial Interface
The ISL59533 is programmed through a three-wire serial
interface. The start and stop conditions are defined by the
ENA signal. While the ENA is low, the data on the SDI (serial
data input) pin is shifted into the 16-bit shift register on the
positive edge of the SCLK (serial clock) signal. The LSB
(bit 0) is loaded first and the MSB (bit 15) is loaded last (see
Table 1). After the full 16-bit data has been loaded, the ENA
is pulled high and the addressed output channel is updated.
The SCLK is disabled internally when the ENA is high. The
SCLK must be low before the ENA is pulled low.
The Serial Timing Diagram and parameters table show the
timing requirements for three-wire signals.
19
FN6222.0
March 13, 2006