ISL54100 Datasheet, PDF (19/21 Pages) Intersil Corporation – TMDS Regenerators with Multiplexers

ISL54100, ISL54101, ISL54102
SCL
SDA
DATA STABLE
DATA CHANGE
DATA STABLE
FIGURE 16. VALID DATA CHANGES ON THE SDA BUS
START Command
Signals the beginning of serial I/O
ISL5410x Serial Bus
R/W
ISL5410x Device Select Address Write
ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 0
The first 7 bits of the first byte select the ISL54100 on the 2-wire
bus at the address set by the ADDR[6:0} pins. The R/W bit is a
0, indicating that the next transaction will be a write.
ISL5410x Register Address Write
A7
A6
A5
A4
A3
A2
A1
A0 _{This is the address of the ISL5410x’s configuration register that}
the following byte will be written to.
ISL5410x Register Data Write(s)
D7
D6
D5
D4
D3
D2
D1
D0 _{This is the data to be written to the ISL5410x’s configuration register.}
(Repeat if desired)
Note: The ISL5410x’s Configuration Register’s address pointer auto
increments after each data write: repeat this step to write multiple
sequential bytes of data to the Configuration Register.
Signals from
the Host
SDA Bus
Signals from
the ISL5410x
STOP Command
Signals the ending of serial I/O
S
T _{Serial Bus}
A
R
Address
T
Register
Address
Data
Write*
S
T
* The data write step may be repeated to write to the
O ISL5410x’s Configuration Register sequentially, beginning at
P _{the Register Address written in the previous step.}
a a a a a a a 0 AAAAAAAA d d d d d d d d
A
A
A
C
C
C
K
K
K
FIGURE 17. CONFIGURATION REGISTER WRITE
19
FN6275.5
June 4, 2008