ISL54100 Datasheet, PDF (16/21 Pages) Intersil Corporation – TMDS Regenerators with Multiplexers

ISL54100, ISL54101, ISL54102
FIGURE 9. ISL54100 EYE DIAGRAM AFTER 15m CABLE
Tx Loading Considerations
When the ISL54100 is powered-up and its Tx outputs are
disabled, via either the PD (power down) pin, the
power-down register bit (register 0x02[5]), or the tri-state
outputs bits (register 0x05[1:0]), the Tx pins are high
impedance. In this state they will draw no current from the
Rx pins of any TMDS receiver they may be connected to.
However if power to the ISL54100 is removed, the Tx pins
are no longer high-impedance. Figure 10 shows the relevant
equivalent circuit, including the internal ESD protection
diodes. For simplicity, only one of the eight Tx outputs, ESD
protection diodes, and Rx termination resistors are shown.
When V_D to the ISL54100 drops below ~2.7V and power is
applied to the external TMDS receiver, ESD protection
diodes inside the ISL54100 can become forward-biased,
drawing current from the external TMDS receiver it is
attached to.
3.3V_TX
V_D
3.3V_RX
Rx_N
50
V_D_ESD ^{(74, 95)}
Tx
Tx_N
ISL5410x
FIGURE 10. ISL5410x ESD PROTECTION DIODES
This is non-ideal and will cause the ISL5410x to fail HDMI
Compliance Test 7-3 (“V_OFF”). V_OFF is the voltage across
each 50Ω Rx_N resistor when the power is removed from the
device containing the ISL54100.
Modifying the PCB layout per Figure 11 to add a Schottky
diode between the V_D power net and the V_D_ESD pins,
eliminates current flow from the ESD bus into V_D. This
reduces the amount of current drawn from the Tx supply, but
there is still some circuitry attached to the internal ESD bus
that will sink some current. So the current drawn from Rx will
be lower than if the diode were not there (reducing the V_OFF
magnitude), but still not low enough to pass Test 7-3.
3.3V_TX
V_D
3.3V_RX
Rx_N
50
D₁
V_D_ESD ^{(74, 95)}
C₁
0.1μF
Tx
Tx_N
ISL5410x
FIGURE 11. SCHOTTKY DIODE MODIFICATION
Intersil is currently sampling the ISL54100A, the ISL54101A,
and the ISL54102A, all of which are fully compliant with Test
7-3 when applied using the circuit shown in Figure 11. These
“A” versions are 100% drop-in compatible with the original
version with the sole exception of the CH_SEL_0 and
CH_SEL_1 pins, which are bidirectional on the original
version but become inputs only on the A version.
Using the new version in a layout designed for the original
version (Figure 10) will result in the same behavior as the
original version (unless you are using the CH_SEL pins as
outputs). See Table 2 for the full matrix.
TABLE 2. VERSION/LAYOUT MATRIX
VERSION
Figure 10
Figure 11
ISL5410x
Fails 7-3,
Fails 7-3 (not as badly)
CH_SEL pins are bidirectional CH_SEL pins are bidirectional
ISL5410xA
Fails 7-3,
Passes 7-3,
CH_SEL pins are input only CH_SEL pins are input only
Intersil recommends adding the Schottky circuit to all
designs to reduce Rx current drain in systems using the
original version and completely eliminate it in systems using
the “A” version.
PCB Layout Recommendations
Because of the high speed of the TMDS signals, careful
PCB layout is critical to maximize performance. The
following guidelines should be adhered to as closely as
possible:
• All TMDS pair traces should have a characteristic
impedance of 50Ω with respect to the power/ground
16
FN6275.5
June 4, 2008