ISL28107_1110 Datasheet, PDF (19/32 Pages) Intersil Corporation – Precision Single, Dual and Quad Low Noise Operational Amplifiers

ISL28107, ISL28207, ISL28407
Typical Performance Curves V_S = ±15V, V_CM = 0V, R_L = Open, T_A = +25°C unless otherwise specified. (Continued)
0.08
0.06
0.04
V_S = ±5V, ±15V, ±20V
0.02
0.00
0.26
0.22
0.18
0.14
0.10
15
V_S = ±15V
R_L = 10k
13
C_L = 4pF
A_V = 100
11
R_f = 10k, R_g = 100
V_IN = 200mV_P-P
9
7
-0.02
-0.04
-0.06
-0.08
0
R_L = 2k, 10k
C_L = 4pF
A_V = 1
V_OUT = 100mV_P-P
5 10 15 20 25 30 35 40
TIME (µs)
0.06
0.02
-0.02
-0.06
0
5
INPUT
3
OUTPUT
1
-1
20 40 60 80 100 120 140 160 180 200
TIME (µs)
FIGURE 51. SMALL SIGNAL TRANSIENT RESPONSE V_S = ±5V,
±15V, ±20V
FIGURE 52. POSITIVE OUTPUT OVERLOAD RESPONSE TIME,
V_S = ±15V
0.06
0.02
-0.02
OUTPUT
1
-1
INPUT
-3
-0.06
-5
-0.10
-0.14
-0.18
-0.22
-0.26
0
-7
V_S = ±15V
R_L = 10k
-9
C_L = 4pF
A_V = 100
-11
R_f = 10k, R_g = 100
V_IN = 200mV_P-P
-13
-15
20 40 60 80 100 120 140 160 180 200
TIME (µs)
FIGURE 53. NEGATIVE OUTPUT OVERLOAD RESPONSE TIME,
V_S = ±15V
Applications Information
Functional Description
The ISL28107, ISL28207 and ISL28407 are single, dual and
quad, very low 1/f noise (14nV/√Hz @ 10Hz) precision op-amps.
These amplifiers feature very high open loop gain (50kV/mV) for
excellent CMRR (145dB) and gain accuracy. Both devices are
fabricated in a new precision 40V complementary bipolar DI
process.
The super-beta NPN input stage with bias current cancellation
provides bipolar-like levels of AC performance, with the low input
bias currents approaching JFET levels. The temperature
stabilization provided by bias current cancellation removes the
high input bias current temperature coefficient commonly found
in JFET amplifiers. Figures 9 and 10 show the input bias current
variation over temperature.
The input offset voltage (V_OS) has a very low, worst case value of
75µV max at +25°C and a maximum T_C of 0.65µV/°C. Figure 38
shows V_OS as a function of supply voltage and temperature with
the common mode voltage at 0V for split supply operation.
50
45
V_S = ±15V
R_L = 10k
40 ^AV ^{= 1}
35 ^{VOUT = 100mVP-P}
30
25
20
OVERSHOOT ⁺
OVERSHOOT ^-
15
10
5
0
1
10
100
1,000
10,000
CAPACITANCE (pF)
FIGURE 54. % OVERSHOOT vs LOAD CAPACITANCE, V_S = ±15V
The complementary bipolar output stage maintains stability
driving large capacitive loads (to 10nF) without external
compensation. The small signal overshoot vs. load capacitance is
shown in Figure 54.
Operating Voltage Range
The devices are designed to operate over the 4.5V (±2.25V) to
40V (±20V) range and are fully characterized at 10V (±5V) and
30V (±15V). Both DC and AC performance remain virtually
unchanged over the complete 4.5V to 40V operating voltage
range. Parameter variation with operating voltage is shown in the
“Typical Performance Curves” beginning on page 11. The input
common mode voltage range sensitivity to temperature is shown
in Figure 38 (±15V).
Input ESD Diode Protection
The input terminals (IN+ and IN-) each have internal ESD
protection diodes to the positive and negative supply rails, a series
connected 500Ω current limiting resistor followed by an
anti-parallel diode pair across the input NPN transistors (Circuit 1
in “Pin Descriptions” on page 3).
19
FN6631.5
October 21, 2011