ISL78220ANEZ Datasheet, PDF (18/22 Pages) Intersil Corporation – 6-Phase Interleaved Boost PWM Controller with Light Load Efficiency Enhancement

ISL78220
identify this tri-state signal and turn off both the lower and upper
switches accordingly. For better transient response during phase
dropping, the ISL78220 will gradually reduce the duty cycle of
the phase from steady state to zero, typically within 15 switching
cycles. This gradual dropping scheme will help smooth the
change of the PWM signal and, in turn, will help to stabilize the
system when phase dropping happens.
The ISL78220 also has an automatic phase adding feature
similar to phase dropping, but when doing phase adding there
will not be 15 switching cycles gradually adding. It will add
phases instantly to take care of the increased load condition. The
phase adding scheme is controlled by three factors.
1. The maximum configured phase number
2. The voltage on the IOUT pin (V_IOUT).
3. Individual phase current
Factors 1 and 2 are similar to the phase dropping scheme. If the
V_IOUT is higher than the phase dropping threshold plus the
hysteresis voltage, the dropped phase will be added back one by
one instantly.
The above mentioned phase-adding method can take care of the
condition that the load current increases slowly. However, if the
load is fast increasing the IC will using different phase adding
scheme. The ISL78220 monitors the individual channel current
for all active phases. During phase adding the system will bring
down the pre-set channel current limit to 2/3 of its original value
(160µA). If any of the phase’s sensed current hit the 2/3 of
pre-set channel current limit threshold (i.e: 106.7µA), all the
phases will be added back instantly. After a fixed 1.5ms delay,
the phase dropping circuit will be activated and the system will
react to drop the phase number to the correct value.
During phase adding when either phase hit the pre-set channel
current limit, there will be 200µs blanking time such that per-
channel OCP will not be triggered during this blanking time.
Diode Emulation at Very Light Load Condition
When phase dropping is asserted and the minimum phase
operation is 2 phases, if the load is still reducing and
synchronous boost structure is used, the ISL78220 controller will
enter into forced cycle-by-cycle diode emulation mode. The PWM
output will be tri-stated when inductor current falls to zero, such
that the synchronous MOSFET can be turned off accordingly
cycle-by-cycle for forced diode emulation. This cycle-by-cycle
diode emulation scheme will only be asserted when two
conditions are met:
1. The PWM_TRI pin voltage is logic HIGH.
2. Only two phases are running either by phase dropping or
initial configuration.
By utilizing the cycle-by-cycle diode emulation scheme in this
way, negative current is prevented and the system can still
optimize the efficiency even at very light load condition.
Pulse Skipping at Deep Light Load Condition
If the converter enters diode emulation mode and the load is still
reducing, eventually pulse skipping will occur to increase the
deep light load efficiency.
Adjustable Slope Compensation
For a boost converter working in current mode control, slope
compensation is needed when steady state duty cycle is larger
than 50%. When slope compensation is too low the converter
can suffer from jitter or oscillation. On the other hand, over
compensation of the slope will cause the reduction of the phase
margin. Therefore, proper design of the slope compensation is
needed.
The ISL78220 features adjustable slope compensation by
setting the resistor value R_SLOPE from the SLOPE pin to GND.
This function will ease the compensation design and provide
more flexibility in choosing the external components.
For current mode control, typically we need the compensation
slope m_A to be 50% of the inductor current down ramp slope m_B
when the lower MOSFET is off. The equation for choosing the
suitable resistor value is as follows:
R_SLOPE
=
1_----._-1_----3_----6_---x_{----1---0----}⁶_---x_---L_----x_---R_{----S---E---T-}
(V_OUT – V_IN)(R_SEN)
(
Ω)
(EQ. 9)
Fault Monitoring and Protection
The ISL78220 actively monitors input/output voltage and current to
detect fault conditions. Fault monitors trigger protective measures
to prevent damage to the load. Common power-good indicator pin
(PGOOD pin) and VIN_OVB, VOUT_OVB pins are provided for linking
to external system monitors.
PGOOD Signal
The PGOOD pin is an open-drain logic output to indicate that the
soft-start period is completed and the output voltage is within the
specified range. This pin is pulled low during soft-start and
releases high after a successful soft-start. PGOOD will be pulled
low when a UV/OV/OC/OT fault occurs.
Input Overvoltage Detection
The ISL78220 utilizes VIN_SEN and VIN_OVB pins to deal with a
high input voltage. The VIN_SEN pin is used for sensing the input
voltage. A resistor divider network is connected between this pin
and the boost power stage input voltage rail. When the voltage
on VIN_SEN is higher than 2.4V, the open drain output VIN_OVB
pin will be pulled low to indicate an input overvoltage condition,
The V_IN overvoltage sensing threshold can be programmed by
changing the resistor values, and hysteresis voltage of the
internal comparator is fixed to be 100mV.
Output Undervoltage Detection
The undervoltage threshold is set at 80% of the internal voltage
reference. When the output voltage at FB pin is below the
undervoltage threshold minus the hysteresis, PGOOD is pulled
low. When the output voltage comes back to 80% of the
reference voltage, PGOOD will return back to high.
Output Overvoltage Detection/Protection
The ISL78220 overvoltage detection circuit monitors the FB pin
and is active after time t₂ in Figure 14. The OV trip point is set to
120% of the internal reference level. Once an overvoltage
condition is detected, the PGOOD will be pulled low but the
controller will continue to operate.
18
FN7688.3
December 24, 2013