ISL78220ANEZ Datasheet, PDF (16/22 Pages) Intersil Corporation – 6-Phase Interleaved Boost PWM Controller with Light Load Efficiency Enhancement

ISL78220
Soft-Start Ramp Slew Rate
Calculation
The soft-start ramp slew rate SR_SS is determined by the capacitor
value C_SS from SS pin to GND. C_SS can be calculated based on
Equation 3:
SR_SS
=
5_----X_{----1----0---}^–_---¹_---²_--
C_SS
⎛
⎝
μ^--V--s^{--⎠⎞}
(EQ. 3)
Figure 18 shows the relationship between C_SS and SR_SS.
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
1
10
100
Css (nF)
FIGURE 18. SOFT- START CAPACITOR vs SLEW RATE
Oscillator and Synchronization
The switching frequency is determined by the selection of the
frequency-setting resistor, R_FS, connected from FS pin to GND.
Equation 4 is provided to assist in selecting the correct resistor
value.
R_FS
=
4
X
10¹⁰
⎛
⎝
----¹-----
f_SW
–
5
X
10^–8_⎠⎞
(EQ. 4)
where f_SW is the switching frequency of each phase. Figure 19
shows the relationship between Rfs and switching frequency.
1000
900
800
700
600
500
400
300
200
100
0
0
100
200
300
400
500
600
R_FS (kΩ)
FIGURE 19. R_FS vs SWITCHING FREQUENCY
The maximum frequency at each PWM output is 1MHz. If the FS
pin is accidentally shorted to GND or connected to a low
impedance node, the internal circuits will detect this fault
condition and fold back the switching frequency to the 75kHz
minimal value.
The ISL78220 contains a phase lock loop (PLL) circuit and has
frequency synchronization capability by simply connecting SYNC
pin to an external square pulse waveform (typically 20% to 80%
duty cycle). In normal operation, the external SYNC frequency
needs to be at least 20% faster than the internal oscillator
frequency setting. The ISL78220 will synchronize its switching
frequency to the fundamental frequency of the input waveform.
The frequency synchronization feature will synchronize the rising
edge of the PWM1 clock signal with the rising edge of the
external clock signal at the SYNC pin.
The PLL is compensated with a series resistor-capacitor (Rc and
Cc) from the PLL_COMP pin to GND and a capacitor (Cp) from
PLL_COMP to GND. Typical values are Rc = 6.8kΩ, Cc = 6.8nF,
Cp = 1nF. The typical lock time is around 0.5ms.
The CLK_OUT pin provides a square pulse waveform at the
switching frequency. The amplitude is 5V with approximately
40% positive duty cycle, and the rising edge is synchronized with
the leading edge of PWM1.
Current Sensing
The ISL78220 senses the current continuously for fast response.
It supports both sense resistor and inductor DCR current sensing
methods. The sensed current for each active channel will be used
for loop control, phase current balance, individual channel
overcurrent protection and total average current protection. The
internal circuitry, shown in Figures 20 and 21, represents a single
channel. This circuitry is repeated for each channel, but may not
be active depending on the status of the PWM3, PWM4, PWM5,
and PWM6 pin voltage.
Peak current mode control is implemented by feeding back the
current output of the current sense amplifier (CSA) to the
regulator control loop. Individual channel peak current limit is
implemented by comparing the CSA output current with 160µA.
When the peak current limit comparator is tripped, the PWM
on-pulse is terminated and the IC is latched off.
Sense Resistor Current Sensing
A sense resistor can be placed in series with the power inductor.
As shown in Figure 20, The ISL78220 acquires the channel
current information by sensing the voltage signal across the
sense resistor. Because the voltage on both the positive input
and the negative input of CSA are forced to be equal, the voltage
across R_SET is equivalent to the voltage drop across the R_SEN
resistor. The resulting current into the ISENxP pin is proportional
to the channel current, I_L. Equation 5 for I_SEN is derived where I_L
is the channel current:
I_SEN
=
I_L ⋅
-R----^S----^E----^N---
R_ISET
(EQ. 5)
16
FN7688.3
December 24, 2013