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ISL6731A Datasheet, PDF (18/20 Pages) Intersil Corporation – Power Factor Correction Controllers | |||
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ISL6731A, ISL6731B
The output feedback resistor divider gain, GDIV is:
GDIV= V-V----OR----EU----FT--
(EQ. 77)
The compensation gain uses external impedance networks as
shown in Figure 18, ZCOMP(s) is given by:
ZCOMPï¨sï©= ï¨---C-----v---c----+----1-C----v---p----ï©---ï---s- ï· -R---------v------cC--R------ï·--vv------cc-C-------+ï·--v------c--CC------ï·--v-v-----c-pC-------ï·--v------p--s----ï·+----s-1----+----1--
(EQ. 78)
The targeted crossover frequency, FCV is 7.5Hz. The high
frequency pole, FPV, is required in order to reject the 2 time line
frequency component. FPV = 20Hz. The targeted phase margin
is 50°.
60
FZV
40
20
FPV
GmV*ZCOMP (s)
FCV
Gps (s)
Choose components from the standard values. We have
CVP = 150nF, CVC = 1µF, RVC = 62kΩ. The actual bode plot is
shown in Figure 20.
40
FCV
120Hz
20
0
0
-20
90
FCV
60
30
120Hz
60
45
0
-20
-40
GDIV
GVLOOP (s)
01
10
100
1k
FREQUENCY (Hz)
FIGURE 20. BODE PLOT OF THE ACTUAL VOLTAGE LOOP GAIN
-60 1
10
100
1k
FREQUENCY (Hz)
FIGURE 19. ASYMPTOTIC BODE PLOT OF VOLTAGE LOOP GAIN
The zero, FZv is calculated:
FZv = -t--a---n----ï¨--ï-----m------+-----a----t-a-F---n-C---ï¨-V-F----C----V-----ï¤---ï¨--F----P----V----ï©--ï©---ï©
(EQ. 79)
FZv = -t--a---n----ï¨--5----0----d---e----g-----+-----a----t-a-7---n.--5--ï¨--Hï¨--7---z-.-5----H-----z---ï©----ï¤--ï¨---2---0----H-----z---ï©---ï©---ï© = 2.648Hz
(EQ. 80)
Then the total capacitance used for compensation is calculated:
Cvc + Cvp = --G-----P----S----ï¨--i---ï·----ï¨---2----ï°---ï¨F---2-C--ï°--V--F--ï©--C-ï©---V--ï·--ï©--G-----D----I--V-----ï·----G-----m------v- ï·
ï¨-ï¨--FF----CC----VV-----ï¤ï¤---FF---P-Z---VV----ï©ï©--2-2----++-----11--
(EQ. 81)
Thus, the total compensation capacitance is:
Cvc + Cvp = 1127nF
Cvp = 1127nF ï· F-F---P-Z---VV-- = 149nF
Cvc = 1127nF â 149.1nF = 977nF
Rvc = -2----ï---ï°-----ï---F----Z-1---V-----ï---C----V----C-- = 61.5kï
(EQ. 82)
(EQ. 83)
(EQ. 84)
(EQ. 85)
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FN8582.1
February 13, 2015
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