ISL28134IBZ Datasheet, PDF (18/25 Pages) Intersil Corporation – 5V Ultra Low Noise, Zero Drift Rail-to-Rail Precision Op Amp

ISL28134
*ISL28134 Macromodel
*
*Revision History:
* Revision A, LaFontaine June 17th 2011
* Model for Noise, quiescent supply currents,
*CMRR135dB f = 200Hz, AVOL 174dB f =
*6.5mHz, SR = 1.5V/us, GBWP 3.5MHz.
*Copyright 2011 by Intersil Corporation
*Refer to data sheet “LICENSE STATEMENT”
*Use of this model indicates your acceptance
*with the terms and provisions in the License
*Statement.
*
*Intended use:
*This Pspice Macromodel is intended to give
*typical DC and AC performance
*characteristics under a wide range of
*external circuit configurations using
*compatible simulation platforms – such as
*iSim PE.
*
*Device performance features supported by
*this model:
*Typical, room temp., nominal power supply
*voltages used to produce the following
*characteristics:
*Open and closed loop I/O impedances,
*Open loop gain and phase,
*Closed loop bandwidth and frequency
*response,
*Loading effects on closed loop frequency
*response,
*Input noise terms including 1/f effects,
*Slew rate, Input and Output Headroom limits
*to I/O voltage swing, Supply current at
*nominal specified supply voltages,
*Output current limiting (65mA)
*
*Device performance features NOT
*supported by this model:
*Harmonic distortion effects,
*Disable operation (if any),
*Thermal effects and/or over temperature
*parameter variation,
*Performance variation vs. supply voltage,
*Part to part performance variation due to
*normal process parameter spread,
*Any performance difference arising from
*different packaging,
*Load current reflected into the power supply
*current.
* source ISL28134
*
* Connections:
*
*
*
*
*
+input
| -input
| | +Vsupply
| | | -Vsupply
| | | | output
| | || |
.subckt ISL28134 Vin+ Vin- V+ V- VOUT
*
*Voltage Noise
E_En VIN+ EN 28 0 1
D_D13 29 28 DN
V_V9 29 0 0.14
R_R21 28 0 80
*
*Input Stage
M_M10 11 VIN- 9 9 PMOSISIL
M_M11 12 1 10 10 PMOSISIL
M_M14 3 1 5 5 NCHANNELMOSFET
M_M15 4 VIN- 6 6 NCHANNELMOSFET
I_I1
7 V-- DC 5e-3
I_I2
V++ 8 DC 5e-3
I_IOS VIN- 1 DC 240e-12
G_G1A V++ 14 4 3 233.4267
G_G2A V-- 14 11 12 233.4267
V_V1
V++ 2 1e-6
V_V2
13 V-- 1e-6
V_VOS EN 30 0.2E-6
R_R1
3 2 7.5004
R_R2
4 2 7.5004
R_R3
5 7 10
R_R4
7 6 10
R_R5
9 8 10
R_R6
8 10 10
R_R7
13 11 7.5
R_R8
13 12 7.5
R_RA1 14 V++ 1
R_RA2 V-- 14 1
C_CinDif VIN- EN 4.71e-12
C_Cin1 V-- 30 10.1e-12
C_Cin2 V-- VIN- 10.1e-12
*
*1st Gain Stage
G_G1 V++ 16 15 VMID 113.96e-3
G_G2 V-- 16 15 VMID 113.96e-3
V_V3 17 16 0.607
V_V4 16 18 0.607
D_D1 15 VMID DX
D_D2 VMID 15 DX
D_D3 17 V++ DX
D_D4 V-- 18 DX
R_R9 15 14 100
R_R10 15 VMID 1e9
R_R11 16 V++ 1
R_R12 V-- 16 1
*
*2nd Gain Stage
G_G3 V++ VG 16 VMID 68.225E-3
G_G4 V-- VG 16 VMID 68.225E-3
V_V5 19 VG 0.607
V_V6 VG 20 0.607
D_D5 19 V++ DX
D_D6 V-- 20 DX
R_R13 VG V++ 7346.06E6
R_R14 V-- VG 7346.06E6
C_C2 VG V++ 3.33E-09
C_C3 V-- VG 3.33E-09
*
*Mid supply Ref
E_E4 VMID V-- V++ V-- 0.5
*
*Supply Isolation Stage
E_E2 V++ 0 V+ 0 1
E_E3 V-- 0 V- 0 1
I_ISY V+ V- DC 675E-6
*
*Common Mode Gain Stage
G_G5 V++ VC VCM VMID 177.83E-6
FIGURE 47. SPICE NET LIST
G_G6 V-- VC VCM VMID 177.83E-6
E_EOS 1 30 VC VMID 1
R_R15 VC 21 1.00E-03
R_R16 22 VC 1.00E-03
R_R22 EN VCM 5e11
R_R23 VCM VIN- 5e11
L_L1 21 V++ 7.957E-07
L_L2 22 V-- 7.957E-07
*
*2nd Pole Stage
G_G7 V++ 23 VG VMID 879.62E-6
G_G8 V-- 23 VG VMID 879.62E-6
R_R17 23 V++ 1136.85
R_R18 V-- 23 1136.85
C_C4 23 V++ 10e-12
C_C5 V-- 23 10e-12
*
*Output Stage
G_G9 26 V-- VOUT 23 20e-3
G_G10 27 V-- 23 VOUT 20e-3
G_G11 VOUT V++ V++ 23 20e-3
G_G12 V-- VOUT 23 V-- 20e-3
V_V7 24 VOUT 1.04
V_V8 VOUT 25 1.04
D_D7 23 24 DX
D_D8 25 23 DX
D_D9 V++ 26 DX
D_D10 V++ 27 DX
D_D11 V-- 26 DY
D_D12 V-- 27 DY
R_R19 VOUT V++ 50
R_R20 V-- VOUT 50
*
.model pmosisil pmos (kp=16e-3 vto=-0.6
+kf=0 af=1)
.model NCHANNELMOSFET nmos (kp=3e-3
+vto=0.6 kf=0 af=1)
.model DN D(KF=6.69e-9 af=1)
.MODEL DX D(IS=1E-12 Rs=0.1 kf=0 af=1)
.MODEL DY D(IS=1E-15 BV=50 Rs=1 kf=0
+af=1)
.ends ISL28134
18
FN6957.3
December 22, 2011