ISL6262CRZ-T Datasheet, PDF (17/27 Pages) Intersil Corporation – Two-Phase Core Regulator for IMVP-6 Mobile CPUs

ISL6262
While transitioning to single-phase operation, the controller
smoothly transitions current from the idling-phase to the
active-phase, and detects the idling-phase zero-current
condition. During transitions into automatic-DCM or forced-
CCM mode, the timing is carefully adjusted to eliminate
output voltage excursions. When a phase is added, the
current balance between phases is quickly restored.
While PSI# is high, both phases are switching. If PSI# is
asserted low and either DPRSTP# or DPRSLPVR are not
asserted, the controller will transition to CCM operation with
only phase 1 switching, and both FET's of phase 2 will be off.
The controller will thus eliminate switching losses associated
with the unneeded channel.
V_OUT & V_SOFT
-2.5mV/µs
10mV/µs
DPRSLPVR
2.5mV/µs
VID #
FIGURE 29. DEEPER SLEEP TRANSITION SHOWING
DPRSLPVR'S EFFECT ON EXIT SLEW RATE
When PSI#, DPRSTP#, and DPRSLPVR are all asserted,
the controller will transition to single-phase DCM mode. In
this mode, both FET's associated with phase 2 will be off,
and the ISL6262 will turn-off the lower FET of channel 1
whenever the channel 1 current decays to zero. As load is
further reduced, the phase 1 channel switching frequency
will decrease, thus maintaining high efficiency.
Dynamic Operation
Refer to Figure 29, the ISL6262 responds to changes in VID
command voltage by slewing to new voltages with a dV/dt
set by the SOFT capacitor and by the state of DPRSLPVR.
With C_SOFT = 15nF and DPRSLPVR HIGH, the output
voltage will move at ±2.8mV/s for large changes in voltage.
For DPRSLPVR LOW, the large signal dV/dt will be
±13mV/s. As the output voltage approaches the VID
command value, the dV/dt moderates to prevent overshoot.
Keeping DPRSLPVR HIGH for voltage transitions into and
out of Deeper Sleep will result in low dV/dt output voltage
changes with resulting minimized audio noise. For fastest
recovery from Deeper Sleep to Active mode, holding
DPRSLPVR LOW will result in maximum dV/dt. Therefore,
the ISL6262 is IMVP-6 compliant for DPRSTP# and
DPRSLPVR logic.
Intersil's R³ Technology™ has intrinsic voltage feedforward.
As a result, high-speed input voltage steps do not result in
significant output voltage perturbations. In response to load
current step increases, the ISL6262 will transiently raise the
switching frequency so that response time is decreased and
current is shared by two channels.
Protection
The ISL6262 provides overcurrent, overvoltage, under-
voltage protection and over-temperature protection as
shown in Table 3.
Overcurrent fault
Way-Overcurrent fault
Overvoltage fault (1.7V)
Overvoltage fault (+200mV)
Undervoltage fault
(-300mV)
Unbalance fault
(7.5mV)
Over-temperature
fault (NTC <1.18V)
TABLE 3. FAULT-PROTECTION SUMMARY OF ISL6262
FAULT DURATION PRIOR
TO PROTECTION
PROTECTION ACTIONS
120µs
PWM1, PWM2 three-state,
PGOOD latched low
<2µs
PWM1, PWM2 three-state,
PGOOD latched low
Immediately
Low-side FET on until Vcore
<0.85V, then PWM three-state,
PGOOD latched low (OV-1.7V
always)
1ms
PWM1, PWM2 three-state,
PGOOD latched low
1ms
PWM1, PWM2 three-state,
PGOOD latched low
1ms
PWM1, PWM2 three-state,
PGOOD latched low
Immediately
VR_TT# goes low
FAULT RESET
VR_ON toggle or VDD toggle
VR_ON toggle or VDD toggle
VDD toggle
VR_ON toggle or VDD toggle
VR_ON toggle or VDD toggle
VR_ON toggle or VDD toggle
N/A
17
FN9199.2
May 15, 2006