ISL3330_14 Datasheet, PDF (17/25 Pages) Intersil Corporation – 3.3V, ±15kV ESD Protected, Dual Protocol (RS-232/RS-485) Transceivers

ISL3330, ISL3331
ISL3331 (QFN Package) Special Features
Logic Supply (V_L Pin)
The ISL3331 (QFN) includes a V_L pin that powers the logic
inputs (Tx inputs and control pins) and Rx outputs. These
pins interface with “logic” devices such as UARTs, ASICs,
and µcontrollers, and today many of these devices use
power supplies significantly lower than 3.3V. Thus, a 3.3V
output level from a 3.3V powered dual protocol IC might
seriously overdrive and damage the logic device input.
Similarly, the logic device’s low V_OH might not exceed the
V_IH of a 3.3V powered dual protocol input. Connecting the
V_L pin to the power supply of the logic device (as shown in
Figure 11) limits the ISL3331’s Rx output V_OH to V_L (see
Figure 14) and reduces the Tx and control input switching
points to values compatible with the logic device output
levels. Tailoring the logic pin input switching points and
output levels to the supply voltage of the UART, ASIC, or
µcontroller eliminates the need for a level shifter/translator
between the two ICs.
V_CC = +3.3V
V_CC = +2V
R_A ^{VOH = 3.3V}
R_XD
ESD
DIODE
GND
V_IH ≥ 2
D_Y
V_OH ≤ 2 ^TXD
GND
ISL3330
V_CC = +3.3V
UART/PROCESSOR
V_CC = +2V
V_L
R_A ^{VOH = 2V}
R_XD
ESD
DIODE
GND
V_IH = 1.4V
D_Y
T_XD
V_OH ≤ 2
GND
ISL3331
UART/PROCESSOR
FIGURE 11. USING V_L PIN TO ADJUST LOGIC LEVELS
V_L can be anywhere from V_CC down to 1.2V, but the input
switching points may not provide enough noise margin when
V_L < 1.5V. Table 5 indicates typical V_IH and V_IL values for
various V_L voltages so the user can ascertain whether or not
a particular V_L voltage meets his needs.
.
TABLE 5. V_IH AND V_IL vs V_L FOR V_CC = 3.3V
V_L (V)
1.2
V_IH (V)
0.85
V_IL (V)
0.26
1.5
0.9
0.5
1.8
0.9
0.73
2.3
1.2
1.0
2.7
1.4
1.3
3.3
1.8
1.7
Note: With V_L ≤ 1.6V, the ISL3331 may not operate at the full
data rate unless the logic signal V_IL is at least 0.2V below
the typical value listed in Table 5.
The V_L supply current (I_L) is typically less than 35µA, as
shown in Figures 19 and 20. All of the DC V_L current is due
to inputs with internal pull-up resistors (SPB, SLEW, RXEN)
being driven to the low input state. The worst case I_L current
occurs when all three of the inputs are low (see Figure 19),
due to the I_L through the pull-up resistors. I_IL through an
input pull-up resistor is ~10µA, so the I_L in Figure 19 drops
by about 18µA (at V_L = 3.3V) when the SPB is high and 232
mode disables the SLEW pin pull-up (middle vs top curve).
When all three inputs are driven high, I_L drops to ~10nA.
Thus, to minimize power dissipation, drive these inputs high
when unneeded (e.g., SPB isn’t used in RS-232 mode, so
drive it high).
QFN logic input pins that are externally tied high in an
application, should use the V_L supply for the high voltage
level.
Active Low Rx Enable (RXEN)
In many RS-485 applications, especially half duplex
configurations, users like to accomplish “echo cancellation”
by disabling the corresponding receiver while its driver is
transmitting data. This function is available on the QFN
package via an active low RXEN pin. The active low function
also simplifies direction control by allowing a single Tx/Rx
direction control line. If the active high RXEN were used,
either two valuable I/O pins would be used for direction
control, or an external inverter is required between DEN and
RXEN. Figure 12 details the advantage of using the RXEN
pin. When using RXEN, ensure that RXEN is tied to GND.
RS-485 Slew Rate Limited Data Rates
The ISL333x FAST speed option (SLEW = High) utilizes Tx
output transitions optimized for a 20Mbps data rate. These
fast edges may increase EMI and reflection issues, even
though fast transitions aren’t required at the lower data rates
used by many applications. With the SLEW pin low, both
product types switch to a moderately slew rate limited output
transition targeted for 460kbps (MED) data rates. The
ISL3331 (QFN version), offers an additional slew rate limited
data rate that is optimized for 115kbps (SLOW), and is
selected when SLEW = 0 and SPB = 0 (see Table 3). The
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FN6361.0
May 20, 2008