HI7190 Datasheet, PDF (17/24 Pages) Intersil Corporation – 24-Bit, High Precision, Sigma Delta A/D Converter

HI7190
TABLE 6. INTERNAL DATA ACCESS DECODE STARTING BYTE
FSC A3 A2 A1 A0
DESCRIPTION
X 0 0 0 0 Data Output Register, Byte 0
X 0 0 0 1 Data Output Register, Byte 1
X 0 0 1 0 Data Output Register, Byte 2
X 0 1 0 0 Control Register, Byte 0
X 0 1 0 1 Control Register, Byte 1
X 0 1 1 0 Control Register, Byte 2
X 1 0 0 0 Offset Cal Register, Byte 0
X 1 0 0 1 Offset Cal Register, Byte 1
X 1 0 1 0 Offset Cal Register, Byte 2
0 1 1 0 0 Positive Full Scale Cal Register, Byte 0
0 1 1 0 1 Positive Full Scale Cal Register, Byte 1
0 1 1 1 0 Positive Full Scale Cal Register, Byte 2
1 1 1 0 0 Negative Full Scale Cal Register, Byte 0
1 1 1 0 1 Negative Full Scale Cal Register, Byte 1
1 1 1 1 0 Negative Full Scale Cal Register, Byte 2
Write Operation
Data can be written to the Control Register, Offset Calibra-
tion Register, Positive Full Scale Calibration Register, and
the Negative Full Scale Calibration Register. Write opera-
tions are done using the SDIO, CS and SCLK lines only, as
all data is written into the HI7190 via the SDIO line even
when using the 3-wire configuration. Figures 15 and 16
show typical write timing diagrams.
The communication cycle is started by asserting the CS line
and starting the clock from its idle state. To assert a read
cycle, during the instruction phase of the communication
cycle, the Instruction Byte should be set to a read transfer
(R/W = 0).
When reading the serial port, data is driven out of the
HI7190 on the falling edge of SCLK. Data can be registered
externally on the next rising edge of SCLK.
Read Operation - 2-Wire Transfer
Data can be read from the Data Output Register, Control
Register, Offset Calibration Register, Positive Full Scale Cal-
ibration Register, and the Negative Full Scale Calibration
Register. When configured in two-wire transfer mode, read
operations are done using the SDIO, CS and SCLK lines. All
data is read via the SDIO line. Figures 19 and 20 show
typical 2-wire read timing diagrams.
The communication cycle is started by asserting the CS line
and starting the clock from its idle state. To assert a read cycle,
during the instruction phase of the communication cycle, the
Instruction Byte should be set to a read transfer (R/W = 0).
When reading the serial port, data is driven out of the
HI7190 on the falling edge of SCLK. Data can be registered
externally on the next rising edge of SCLK.
Detailed Register Descriptions
Data Output Register
The Data Output Register contains 24 bits of converted data.
This register is a read only register.
BYTE 2
MSB 22
21
20
19
18
17
16
D23 D22 D21 D20 D19 D18 D17 D16
The communication cycle is started by asserting the CS line
low and starting the clock from its idle state. To assert a write
cycle, during the instruction phase of the communication
cycle, the Instruction Byte should be set to a write transfer
(R/W = 1).
When writing to the serial port, data is latched into the
HI7190 on the rising edge of SCLK. Data can then be
changed on the falling edge of SCLK. Data can also be
changed on the rising edge of SCLK due to the 0ns hold
time required on the data. This is useful in pipelined applica-
tions where the data is latched on the rising edge of the
clock.
BYTE 1
15
14
13
12
11
10
9
8
D15 D14 D13 D12 D11 D10 D9 D8
BYTE 0
7
6
5
4
3
2
1 LSB
D7 D6 D5 D4 D3 D2 D1 D0
Read Operation - 3-Wire Transfer
Data can be read from the Data Output Register, Control
Register, Offset Calibration Register, Positive Full Scale
Calibration Register, and the Negative Full Scale Calibration
Register. When configured in 3-wire transfer mode, read
operations are done using the SDIO, SDO, CS and SCLK
lines. All data is read via the SDO line. Figures 17 and 18
show typical 3-wire read timing diagrams.
1887