ISL6226 Datasheet, PDF (16/17 Pages) Intersil Corporation – Advanced PWM and Linear Power Controller for Portable Applications

ISL6226
capacitor surge current rating. These capacitors must be
capable of handling the surge-current at power-up. The TPS
series available from AVX is surge current tested.
MOSFET Considerations
The logic level MOSFETs are chosen for optimum efficiency
given the potentially wide input voltage range and output
power requirements. One dual N-Channel or Two N-channel
MOSFETs are used in each of the synchronous-rectified
buck converters for the outputs. These MOSFETs should be
selected based upon r_DS(ON) , gate supply requirements,
and thermal management considerations.
The power dissipation includes two loss components;
conduction loss and switching loss. These losses are
distributed between the upper and lower MOSFETs
according to duty cycle (see the following equations). The
conduction losses are the main component of power
dissipation for the lower MOSFETs. Only the upper MOSFET
has significant switching losses, since the lower device turns
on and off into near zero voltage.
P_UPPER
=
I_--O-----²_----×_-----r_{--D----S----(--O-----N----)---}×_-----V_{----O-----U----T-- + -}I_-O------×_-----V_{----I--N-----}×_-----t_{--S----W------}×_-----F_----S--
V_IN
2
P_LOWER
=
I_--O-----²_----×_-----r_{--D----S----(--O-----N----)---}×_-----(_---V_{----I--N-----–----}V_{-----O----U----T----})
V_IN
The equations assume linear voltage-current transitions and
do not model power loss due to the reverse-recovery of the
lower MOSFET’s body diode. The gate-charge losses are
dissipated by the ISL6226 and do not heat the MOSFETs.
However, a large gate-charge increases the switching time,
t_SW which increases the upper MOSFET switching losses.
Ensure that both MOSFETs are within their maximum
junction temperature at high ambient temperature by
calculating the temperature rise according to package
thermal-resistance specifications.
Layout Considerations
MOSFETs switch very fast and efficiently. The speed with
which the current transitions from one device to another
causes voltage spikes across the interconnecting impedances
and parasitic circuit elements. The voltage spikes can
degrade efficiency, radiate noise into the circuit, and lead to
device over voltage stress. Careful component layout and
printed circuit design minimizes the voltage spikes in the
converter. Consider, as an example, the turn-off transition of
one of the upper PWM MOSFETs. Prior to turn-off, the upper
MOSFET is carrying the full load current. During the turn-off,
current stops flowing in the upper MOSFET and is picked up
by the lower MOSFET. Any inductance in the switched current
path generates a voltage spike during the switching interval.
Careful component selection, tight layout of the critical
components, and short, wide circuit traces minimize the
magnitude of voltage spikes. See the Application Note
AN1013 for the evaluation board component placement and
the printed circuit board layout details.
There are two sets of critical components in a DC-DC
converter using an ISL6226 controller. The switching power
components are the most critical because they switch large
amounts of energy, and as such, they tend to generate
equally large amounts of noise. The critical small signal
components are those connected to sensitive nodes or
those supplying critical bias currents.
Power Components Layout Considerations
The power components and the controller IC should be
placed first. Locate the input capacitors, especially the high-
frequency ceramic decoupling capacitors, close to the power
MOSFETs. Locate the output inductor and output capacitors
between the MOSFETs and the load. Locate the PWM
controller close to the MOSFETs.
Insure the current paths from the input capacitors to the
MOSFETs, to the output inductors and output capacitors are
as short as possible with maximum allowable trace widths.
A multi-layer printed circuit board is recommended. Dedicate
one solid layer for a ground plane and make all critical
component ground connections with via to this layer. Dedicate
another solid layer as a power plane and break this plane into
smaller islands of common voltage levels. The power plane
should support the input power and output power nodes. Use
copper filled polygons on the top and bottom circuit layers for
the phase nodes, but do not unnecessarily oversize these
particular islands. Since the phase nodes are subjected to
very high dV/dt voltages, the stray capacitor formed between
these islands and the surrounding circuitry will tend to couple
switching noise. Use the remaining printed circuit layers for
small signal wiring. The wiring traces from the control IC to the
MOSFET gate and source should be sized to carry 2A peak
currents.
Small Components Signal Layout Considerations
The Vin pin 1 input should be bypassed with a 1.0uF
capacitor. The bypass capacitors for Vin and the soft-start
capacitor, should be located close to their connecting pins on
the control IC.
Refer to the Application Note AN1013 for a recommended
component placement and interconnections.
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