ISL23315 Datasheet, PDF (16/19 Pages) Intersil Corporation – Single, Low Voltage Digitally Controlled Potentiometer (XDCP™)

ISL23315
Write Operation
A Write operation requires a START condition, followed by a valid
Identification Byte, a valid Address Byte, a Data Byte, and a STOP
condition. After each of the three bytes, the ISL23315 responds
with an ACK. The data is transferred from I²C block to the
corresponding register at the 9th clock of the data byte and
device enters its standby state (see Figures 27 and 28).
Read Operation
A Read operation consists of a three byte instruction followed by
one or more Data Bytes (see Figure 29). The master initiates the
operation issuing the following sequence: a START, the
Identification byte with the R/W bit set to “0”, an Address Byte, a
second START, and a second Identification byte with the R/W bit
set to “1”. After each of the three bytes, the ISL23315 responds
with an ACK; then the ISL23315 transmits Data Byte. The master
terminates the read operation issuing a NACK (ACK) and a STOP
condition following the last bit of the last Data Byte (see
Figure 29).
Applications Information
V_LOGIC Requirements
It is recommended to keep V_LOGIC powered all the time during
normal operation. In a case where turning V_LOGIC OFF is
necessary, it is recommended to ground the V_LOGIC pin of the
ISL23315. Grounding the V_LOGIC pin or both V_LOGIC and V_CC does
not affect other devices on the same bus. It is good practice to
put a 1µF cap in parallel to 0.1µF as close to the V_LOGIC pin as
possible.
V_CC Requirements and Placement
It is recommended to put a 1µF capacitor in parallel with 0.1µF
decoupling capacitor close to the V_CC pin.
Wiper Transition
When stepping up through each tap in voltage divider mode,
some tap transition points can result in noticeable voltage
transients, or overshoot/undershoot, resulting from the sudden
transition from a very low impedance “make” to a much higher
impedance “break” within a short period of time (<1µs). There
are several code transitions such as 0Fh to 10h, 1Fh to 20h,...,
EFh to FFh, which have higher transient glitch. Note, that all
switching transients will settle well within the settling time as
stated in the datasheet. A small capacitor can be added
externally to reduce the amplitude of these voltage transients.
However, that will also reduce the useful bandwidth of the circuit,
thus may not be a good solution for some applications. It may be
a good idea, in that case, to use fast amplifiers in a signal chain
for fast recovery.
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FN7778.0
December 15, 2010