HSP50016_14 Datasheet, PDF (16/30 Pages) Intersil Corporation – Digital Down Converter

HSP50016
TABLE 7. PHASE GENERATION/HDF.OUTPUT REGISTER
DESTINATION ADDRESS = 4
BIT
POSITION
FUNCTION
DESCRIPTION
39-37
Address
100 = Control Word 4
36
Update
0 = Update Only This Control Register
1 = Update All Control Registers
35-33
Reserved
All Zeroes
32-31
30-7
Output
Spectrum
00 = No Up Conversion,Complex Output
01 = Up Convert by f”/4, Real Output
10 = Up Convert by f”/2,Complex Output
11 = Reserved Mode
Delta Phase Increment 24-Bit Delta Phase Increment. Bits 30-7 = 2²³... 2⁰.
Range: 0 < Delta Phase Increment < π (2^-8-2^-32)
6-1
HDF Data Shift
16-Bit HDF Gain Compensation Number - the shift portion.
(Shift Factor)
HDF Input Data Shift (Towards LSB). Bits 6-1 = 2⁵...2⁰.
Range: 0 ≤ Shift Factor ≤ 55 decimal; Range: [0 ≤ Shift Factor ≤ 37]hex
Calculate the value for this field using this equation:
HDF Data Shift = [75 - Ceiing(5 log₂(R))]hex
Note: log₂(x) = (3.32)log(x)
0
Spectral Reverse
0 = Normal Output
1 = Spectrally Reversed Output
BIT
POSITION
FUNCTION
39-37
Address
36
Update
35-21
HDF Decimation
Counter Preload
(HDF DCP)
TABLE 8. HDF/OUTPUT REGISTER
DESTINATION ADDRESS = 5
DESCRIPTION
101 = Control Word 5
0 = Update Only This Control Register
1 = Update All Control Registers
HDF Decimation Counter Preload. Range: 15 < HDF Decimation Counter Preload < 32,767
Calculate the value for this feild using this equation:
HDF DCP = R - 1; where R is the HDF decimation (rate change) factor.
Common HDF decimation (rate change) factors and associated hexidecimal HDF DCP values:
000f: R = 16
00ff: R = 128
01ff: R = 512
03ff: R = 1,024
07ff: R = 2,048
0fff: R = 4,096
1fff: R = 8,192
3fff: R = 16,384
7fff: R = 32,768
3-16