80C286_1 Datasheet, PDF (16/60 Pages) Intersil Corporation – High Performance Microprocessor with Memory Management and Protection

80C286
Reserved Memory Locations
The 80C286 reserves two fixed areas of memory in real
address mode (see Figure 7); system initialization area and
interrupt table area. Locations from addresses FFFF0(H)
through FFFFF(H) are reserved for system initialization. Initial
execution begins at location FFFF0(H). Locations 00000(H)
through 003FF(H) are reserved for interrupt vectors.
RESET BOOTSTRAP
PROGRAM JUMP
•••
INTERRUPT POINTER
FOR VECTOR 255
•••
INTERRUPT POINTER
FOR VECTOR 1
INTERRUPT POINTER
FOR VECTOR 0
FFFFFH
FFFF0H
3FFH
3FCH
7H
4H
3H
0H
INITIAL CS:IP VALUE IS F000:FFF0
FIGURE 7. 80C286 REAL ADDRESS MODE INITIALLY
RESERVED MEMORY LOCATIONS
Protected Mode Initialization
To prepare the 80C286 for protected mode, the LIDT instruc-
tion is used to load the 24-bit interrupt table base and 16-bit
limit for the protected mode interrupt table. This instruction
can also set a base and limit for the interrupt vector table in
real address mode. After reset, the interrupt table base is ini-
tialized to 000000(H) and its size set to 03FF(H). These val-
ues are compatible with 80C86 and 80C88 software. LIDT
should only be executed in preparation for protected mode.
Shutdown
Shutdown occurs when a severe error is detected that prevents
further instruction processing by the CPU. Shutdown and halt
are externally signalled via a halt bus operation. They can be
distinguished by A₁ HIGH for halt and A₁ LOW for shutdown. In
real address mode, shutdown can occur under two conditions:
• Exceptions 8 or 13 happen and the IDT limit does not
include the interrupt vector.
• A CALL INT or PUSH instruction attempts to wrap around
the stack segment when SP is not even.
An NMI input can bring the CPU out of shutdown if the IDT
limit is at least 000F(H) and SP is greater than 0005(H), oth-
erwise shutdown can only be exited via the RESET input.
Interrupts
Table 9 shows the interrupt vectors reserved for exceptions
and interrupts which indicate an addressing error. The
exceptions leave the CPU in the state existing before
attempting to execute the failing instruction (except for
PUSH, POP, PUSHA, or POPA). Refer to the next section on
protected mode initialization for a discussion on exception 8.
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