ISL705AEHVF Datasheet, PDF (15/19 Pages) Intersil Corporation – Rad-Hard, 5.0V/3.3V u-Processor Supervisory Circuits

ISL705AEH, ISL705BEH, ISL705CEH, ISL706AEH, ISL706BEH, ISL706CEH
R_PULL=
V_{----P----U---L---L-}
I_SINK
(EQ. 4)
Adding Hysteresis to the PFI Comparator
The PFI comparator has no built in hysteresis, however the
designer may add hysteresis by connecting a resistor from the
PFO pin to the PFI pin, essentially adding positive feedback to the
comparator (see Figure 38).
V_DD
RST
R1
PFI
PFO
R2
ISL705AEH
R3
FIGURE 38. POSITIVE FEEDBACK FOR HYSTERISIS
The following procedure allows the system designer to calculate
the components based on the requirements and on given data,
such as supply rail voltages, hysteresis band voltage (V_HB), and
reference voltage (V_PFI).
The comparator only has two states of operation. When it is low,
the current through R3 is I_R3 = V_PFI/R3. When the output is high,
I_R3 = (V_DD - V_PFI)/R3. The feedback current needs to be very
small so it does not induce oscillations; 200nA is a good starting
point. Now two values of R3 can be calculated with V_DD = 5V and
V_PFI = 1.25V; R3 = 6.25MΩ or 11.25MΩ, select the lowest value
of the two.
With R3 selected as 6.2MΩ (closest standard 1% resistor), R1
can be calculated as:
R1=
R
3
⎛
⎝
-^VV---^H_D----_D-^B--_⎠⎞
=
124 k Ω
(EQ. 5)
with VHB selected at 100mV. The closest standard value for R1 is
124kΩ. Then next step is select the rising trip voltage (VTR) such
that:
VTR
>
V_P
F
I
⎛
⎝
1
+
-^VV---^H_D----_D-^B--_⎠⎞
(EQ. 6)
The rising threshold voltage is selected at 3.0V and R2 is
calculated by Equation 7.
R2
= 1⁄
⎛
⎝
(^---V^---_P^----_F^V---_I^-T--×^-R----R^----1^----)⎠⎞
–
⎛
⎝
R^---1--1^{--⎠⎞}
–
⎝⎛ _R^---1--₃^--⎠⎞
(EQ. 7)
Plugging in all the variables R2 in this example is 90.9kΩ again
this is choosing the closest 1% resistor. The final step is verify the
trip voltages.
VTR
=
(V_PFI) × R1
⎛
⎝
R^---1--1^{--⎠⎞}
+
⎛
⎝
R^---1--2^{--⎠⎞}
+
⎛
⎝
R^---1--3^{--⎠⎞}
(EQ. 8)
VTF
=
V
T
R
–
⎛
⎝
R_-----1_-----R×_----3-V_---D_-----D_{--⎠⎞}
(EQ. 9)
The rising voltage, VTR is calculated as 2.98V and the falling
voltage VTF is calculated as 2.88V so 100mV hysteresis is
achieved.
An additional item to consider is that the output voltage is equal
to V_DD, however according to the “Electrical Specifications” on
page 6, the output of the PFI comparator is guaranteed to be at
least (V_DD-1.5) volts. When you take this worst case into account,
the hysteresis can be as low at 70mV.
Special Application Considerations
Using good decoupling practices will prevent transients (i.e., due
to switching noises and short duration droops in the supply
voltage) from causing unwanted resets and reduce the power-fail
circuit’s sensitivity to high-frequency noise on the line being
monitored.
When the WDI input is left unconnected, it is recommended to
place a 10µF capacitor to ground to reduce single event
transients from arising in the WDO pin.
As described in the “Electrical Specifications” Table on page 7,
there is a delay on the PFO pin whenever PFI crosses the
threshold. This delay is due to internal filters on the PFI
comparator circuitry which were added to mitigate single event
transients. If the PFI input transitions below or above the
threshold and the duration of the transition is less than the delay,
the PFO pin will not change states.
15
FN8262.0
March 30, 2012