ISL6752_06 Datasheet, PDF (15/16 Pages) Intersil Corporation – ZVS Full-Bridge Current-Mode PWM with Adjustable Synchronous Rectifier Control

ISL6752
CT
OUTLL
OUTLR
OUTLLN
(SR1)
OUTLRN
(SR2)
FIGURE 17. WAVEFORM TIMING WITH PWM OUTPUTS
DELAYED, 0V < VADJ < 2.425V
CT
OUTLL
On/Off Control
The ISL6753 does not have a separate enable/disable
control pin. The PWM outputs, OUTLL/OUTLR, may be
disabled by pulling VERR to ground. Doing so reduces the
duty cycle to zero, but the upper 50% duty cycle outputs,
OUTUL/OUTUR, will continue operation. Likewise, the SR
outputs OUTLLN/OUTLRN will be active high.
If the application requires that all outputs be off, then the
supply voltage, VDD, must be removed from the IC. This
may be accomplished as shown below.
+Vdd
ISL6752
VADJ
VREF
VERR
CTBUF
RTD
RESDEL
CT
CS
VDD
OUTLL
OUTLR
OUTUL
OUTUR
OUTLLN
OUTLRN
GND
ON/OFF
(OPEN = OFF
GND = ON)
OUTLR
OUTLLN
(SR1)
OUTLRN
(SR2)
FIGURE 18. WAVEFORM TIMING WITH SR OUTPUTS
DELAYED, 2.575V < VADJ < 5.00V
Setting VADJ to VREF/2 results in no delay on any output.
The no delay voltage has a ±75mV tolerance window.
Control voltages below the VREF/2 zero delay threshold
cause the PWM outputs, OUTLL/LR, to be delayed. Control
voltages greater than the VREF/2 zero delay threshold
cause the SR outputs, OUTLLN/LRN, to be delayed. It
should be noted that when the PWM outputs, OUTLL/LR,
are delayed, the CS to output propagation delay is increased
by the amount of the added delay.
The delay feature is provided to compensate for mismatched
propagation delays between the PWM and SR outputs as
may be experienced when one set of signals crosses the
primary-secondary isolation boundary. If required, individual
output pulses may be stretched or compressed as required
using external resistors, capacitors, and diodes.
When the PWM outputs are delayed, the 50% upper outputs
are equally delayed, so the resonant delay setting is
unaffected.
FIGURE 19. ON/OFF CONTROL USING VDD
Fault Conditions
A fault condition occurs if VREF or VDD fall below their
undervoltage lockout (UVLO) thresholds or if the thermal
protection is triggered. When a fault is detected the outputs
are disabled low. When the fault condition clears the outputs
are re-enabled.
An overcurrent condition is not considered a fault and does
not result in a shutdown.
Thermal Protection
Internal die over temperature protection is provided. An
integrated temperature sensor protects the device should
the junction temperature exceed 140°C. There is
approximately 15°C of hysteresis.
Ground Plane Requirements
Careful layout is essential for satisfactory operation of the
device. A good ground plane must be employed. VDD and
VREF should be bypassed directly to GND with good high
frequency capacitance.
References
[1] Ridley, R., “A New Continuous-Time Model for Current
Mode Control”, IEEE Transactions on Power
Electronics, Vol. 6, No. 2, April 1991.
15
FN9181.2
April 4, 2006