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ISL6752_06 Datasheet, PDF (10/16 Pages) Intersil Corporation – ZVS Full-Bridge Current-Mode PWM with Adjustable Synchronous Rectifier Control
ISL6752
1
16
2 VREF
15
3 VERR
14
R
4
13
5
ISL6752
12
6
11
C
7
10
8
9
FIGURE 5. IMPLEMENTING SOFT-START
The values of R and C should be selected to control the rate
of rise of VERR to the desired soft-start duration. The soft-
start duration may be calculated from Equation. 6.
t
=
–RC
⋅

ln  1

–
V-----R---V--E---S-F---S--+---–--0----V----.--0--b------β0--e----1--------R------
S
(EQ. 6)
where VSS is the soft-start clamp voltage, Vbe is the base-
emitter voltage drop of the transistor, and β is the DC gain of
the transistor. If β is sufficiently large, that term may be
ignored. The schottky diode discharges the soft-start
capacitor so that the circuit may be reset quickly.
Gate Drive
The ISL6752 outputs are capable of sourcing and sinking
10mA (at rated VOH, VOL) and are intended to be used in
conjunction with integrated FET drivers or discrete bipolar
totem pole drivers. The typical on resistance of the outputs is
50Ω.
Overcurrent Operation
The cycle-by-cycle peak current control results in pulse-by-
pulse duty cycle reduction when the current feedback signal
exceeds 1.0V. When the peak current exceeds the
threshold, the active output pulse is immediately terminated.
This results in a well controlled decrease in output voltage as
the load current increases beyond the current limit threshold.
The ISL6752 will operate continuously in an overcurrent
condition.
The propagation delay from CS exceeding the current limit
threshold to the termination of the output pulse is increased
by the leading edge blanking (LEB) interval. The effective
delay is the sum of the two delays and is nominally 105ns.
Slope Compensation
Peak current-mode control requires slope compensation to
improve noise immunity, particularly at lighter loads, and to
prevent current loop instability, particularly for duty cycles
greater than 50%. Slope compensation may be
accomplished by summing an external ramp with the current
feedback signal or by subtracting the external ramp from the
voltage feedback error signal. Adding the external ramp to
the current feedback signal is the more popular method.
From the small signal current-mode model [1] it can be
shown that the naturally-sampled modulator gain, Fm,
without slope compensation, is
Fm = ---------1----------
SnTsw
(EQ. 7)
where Sn is the slope of the sawtooth signal and Tsw is the
duration of the half-cycle. When an external ramp is added,
the modulator gain becomes
Fm
=
(---S----n-----+-----S-1----e---)---T----s---w---
=
-------------1--------------
mcSnTsw
(EQ. 8)
where Se is slope of the external ramp and
mc
=
1 + S-----e--
Sn
(EQ. 9)
The criteria for determining the correct amount of external
ramp can be determined by appropriately setting the
damping factor of the double-pole located at half the
oscillator frequency. The double-pole will be critically
damped if the Q-factor is set to 1, and over-damped for
Q > 1, and under-damped for Q < 1. An under-damped
condition can result in current loop instability.
Q = π----(---m-----c---(--1-----–--1---D-----)---–-----0---.--5----)
(EQ. 10)
where D is the percent of on time during a half cycle. Setting
Q = 1 and solving for Se yields
Se
=
Sn


1--
π
+
0.5
1-----–-1----D---
–
1
(EQ. 11)
Since Sn and Se are the on time slopes of the current ramp
and the external ramp, respectively, they can be multiplied
by TON to obtain the voltage change that occurs during TON.
Ve
=
Vn


1--
π
+
0.5
1-----–-1----D---
–
1
(EQ. 12)
where Vn is the change in the current feedback signal during
the on time and Ve is the voltage that must be added by the
external ramp.
Vn can be solved for in terms of input voltage, current
transducer components, and output inductance yielding
Ve
=
T----S----W-------⋅---V----O------⋅---R----C----S--
NCT ⋅ LO
⋅
N-----S--
NP


1--
π
+
D
–
0.5
V
(EQ. 13)
where RCS is the current sense burden resistor, NCT is the
current transformer turns ratio, LO is the output inductance,
VO is the output voltage, and NS and NP are the secondary
and primary turns, respectively.
10
FN9181.2
April 4, 2006