ISL6565A Datasheet, PDF (15/28 Pages) Intersil Corporation – Multi-Phase PWM Controller with Precision rDS(ON) or DCR Current Sensing for VR10.X Application

ISL6565A, ISL6565B
As shown in Figure 7, a current proportional to the average
current in all active channels, I_AVG, flows from FB through a
load-line regulation resistor, R_FB. The resulting voltage drop
across R_FB is proportional to the output current, effectively
creating an output voltage droop with a steady-state value
defined as
V_DROOP = I_AVG R_FB
(EQ. 10)
In most cases, each channel uses the same component
values to sense current. If this is the case you can derive a
more complete equation for V_DROOP for each current sense
method being used.
V_DROOP
=
-I-^O-----^U----^T--
N
r---_{D----S----(--O----N-----)}
R_ISEN
R_FB
r_DS(ON) SENSING _{(EQ. 11)}
(ISL6565A ONLY)
V_DROOP
=
-^I-^O-----^U----^T--
N
⋅
K
⋅
---^D----^C-----^R-----
R_ISEN
R_FB
DCR SENSING
(EQ. 12)
(ISL6565B ONLY)
Output-Voltage Offset Programming
The ISL6565A, ISL6565B allows the designer to accurately
adjust the offset voltage by connecting a resistor, R_OFS,
from the OFS pin to VCC or GND. When R_OFS is connected
between OFS and VCC, the voltage across it is regulated to
2.0V. This causes a proportional current (I_OFS) to flow into
the OFS pin and out of the FB pin. If R_OFS is connected to
ground, the voltage across it is regulated to 0.5V, and I_OFS
flows into the FB pin and out of the OFS pin. The offset
current flowing through the resistor between VDIFF and FB
will generate the desired offset voltage which is equal to the
product (I_OFS x R_FB). These functions are shown in Figures
8 and 9.
Once the desired output offset voltage has been determined,
use the following formulas to set R_OFS:
For Positive Offset (connect R_OFS to GND):
R_OFS
=
-⁰---^.--⁵-----^×-----^R----^F----^B--
V_OFFSET
(EQ. 13)
For Negative Offset (connect R_OFS to VCC):
R_OFS
=
---²-----^×-----^R-----^F---^B-----
V_OFFSET
(EQ. 14)
VDIFF
+
V_{OFS RFB}
-
VREF
E/A
FB
I_OFS
R_OFS
OFS
GND
ISL6565A, ISL6565B
+
0.5V
-
-
2.0V
+
GND
VCC
FIGURE 8. POSITIVE OFFSET OUTPUT VOLTAGE
PROGRAMMING
VDIFF
-
V_{OFS RFB}
+
VREF
E/A
FB
I_OFS
VCC
R_OFS
OFS
ISL6565A, ISL6565B
+
0.5V
-
-
2.0V
+
GND
VCC
FIGURE 9. NEGATIVE OFFSET OUTPUT VOLTAGE
PROGRAMMING
Dynamic VID
Modern microprocessors need to make changes to their core
voltage as part of normal operation. They direct the core-
voltage regulator to do this by making changes to the VID
inputs. The core-voltage regulator is required to monitor the
DAC inputs and respond to on-the-fly VID changes in a
controlled manner supervising a safe output voltage transition
without discontinuity or disruption.
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