ISL59834 Datasheet, PDF (15/17 Pages) Intersil Corporation – Quad Channel, Single Supply, Video Reconstruction Filter with On-Board Charge Pump

ISL59834
is longer because extra time is needed for the charge pump
to settle before the amplifiers are enabled. When disabled,
the device supply current is reduced to 5µA. Power-down is
controlled by standard TTL or CMOS signal levels at the
ENABLE pins. The applied logic signal is relative to the GND
pin. Applying a signal that is less than 0.8V above GND will
disable the device. The device will be enabled when the
ENABLE signals are 2V above GND.
Output Drive Capability
The maximum output current for the ISL59834 is ±50mA.
Maximum reliability is maintained if the output current never
exceeds ±50mA, after which the electro-migration limit of the
process will be exceeded and the part will be damaged. This
limit is set by the design of the internal metal
interconnections.
Driving Capacitive Loads and Cables
The ISL59834 (internally-compensated to drive 75Ω cables)
will drive 10pF loads in parallel with 150Ω or 75Ω with less
than 1.3dB of peaking.
Power Dissipation
With the high output drive capability of the ISL59834, it is
possible to exceed the +150°C absolute maximum junction
temperature under certain load current conditions.
Therefore, it is important to calculate the maximum junction
temperature for an application to determine if load conditions
or package types need to be modified to assure operation of
the amplifier in a safe operating area.
The maximum power dissipation allowed in a package is
determined according to Equation 1:
PD_MAX = ^T----^J---^M-----^A----^X-_Θ----–-_J---_A-^T----^A---^M-----^A----^X--
(EQ. 1)
Where:
T_JMAX = Maximum junction temperature
T_AMAX = Maximum ambient temperature
Θ_JA = Thermal resistance of the package
The maximum power dissipation actually produced by an IC
is the total quiescent supply current times the total power
supply voltage, plus the power in the IC due to the load, or:
for sourcing:
PD_MAX
=
V_S
×
I_S
M
A
X
+
(
V_S
–
V_O
U
T
i
)
×
---^V----^O----^U----^T----ⁱ--
R_LOADi
(EQ. 2)
for sinking:
PD_MAX = V_S × I_SMAX + (V_OUTi – V_S) × I_LOADi
(EQ. 3)
Where:
V_S = Supply voltage
I_SMAX = Maximum quiescent supply current
V_OUT = Maximum output voltage of the application
R_LOAD = Load resistance tied to ground
I_LOAD = Load current
i = Number of output channels
By setting Equation 1 equal to Equation 2 and 3, we can
solve for the output current and R_LOAD values needed to
avoid exceeding the maximum junction temperature.
Power Supply Bypassing and Printed Circuit
Board Layout
As with any high frequency device, a good printed circuit
board layout is necessary for optimum performance. Strip
line design techniques are recommended for the input and
output signal traces to help control the characteristic
impedance. Furthermore, the characteristic impedance of
the traces should be 75Ω. Trace lengths should be as short
as possible between the output pin and the series 75Ω
resistor. The power supply pin must be well bypassed to
reduce the risk of oscillation. For normal single supply
operation, a single 4.7µF tantalum capacitor in parallel with a
0.1µF ceramic capacitor from V_S and V_CP to GND will
suffice.
The AC performance of this circuit depends greatly on the
care taken in designing the PC board. The following are
recommendations to achieve optimum high frequency
performance from your PC board.
• Use low inductance components, such as chip resistors
and chip capacitors whenever possible.
• Minimize signal trace lengths. Trace inductance and
capacitance can easily limit circuit performance. Avoid
sharp corners; use rounded corners when possible. Vias
in the signal lines add inductance at high frequency and
should be avoided. PCB traces longer than 1" begin to
exhibit transmission line characteristics with signal rise/fall
times of 1ns or less. To maintain frequency performance
with longer traces, use striplines.
• Match channel-to-channel analog I/O trace lengths and
layout symmetry. This will minimize propagation delay
mismatches.
• Route all signal I/O lines over continuous ground planes
(i.e. no split planes or PCB gaps under these lines).
• Place termination resistors in their optimum location as
close to the device as possible.
15
FN6268.1
June 11, 2008