ISL59451 Datasheet, PDF (15/17 Pages) Intersil Corporation – Triple 4:1 DC Restored Single Supply Video Multiplexing Amplifier

ISL59451
Therefore, if V_REF is set to 0V (GND); V_OUT = 15mV, and
the DC voltage stored on CX1 is ~1.6V.
The CX1 capacitor value is chosen from the system
requirements. A typical DC-restore application using an
NTSC video horizontal sync to drive the CLAMP pin will
result in a 62µs hold time. The typical input bias current to
the video amplifier is 1.2µA, so for a 62µs hold time, and a
0.01µF capacitor, the output voltage drift is 7.5mV in one
line. The restore amplifier can provide a typical source
current of 860µA to charge capacitor CX1, so with a 1.2µs
sampling time, the output can be corrected by 36mV in each
line.
Using a smaller value of CX1 increases both the voltage that
can be corrected, as well as the droop while being held.
Likewise, using a larger value of CX1, reduces the correction
and droop voltages. A sample of charging and droop rates
are shown in Table 2.
TABLE 2. TABLE OF CHARGE STORAGE CAPACITOR VS
DROOP CHARGING RATES (NOTE)
CAP VALUE
(nF)
DROOP IN
62µs
(mV)
CHARGE IN
1.2µs
(mV)
CHARGE IN
4µs
(mV)
10
7.5
103
344
33
2.3
32.5
103
100
0.75
10.3
34
V_DROOP
=
-------------^I-^B--------------
CAP Value
×
( Line
Time
–
Sample
Time )
V_CHARGE
=
----^I--^C-----^L---^A----^M----^P------ × (Sample Time)
CAP Value
(EQ. 4)
(EQ. 5)
Figure 36 shows the test setup for measuring the DC
Restore’s response to an input DC step shown in Figures 21
and 22.
1Hz SQUARE WAVE
500Ω
NTSC
VIDEO
75Ω
0.1µF
75Ω
ISL59451
CLAMP
OUTPUT
150Ω
NTSC HSYNC
TIMING
FIGURE 36. DC STEP RESPONSE
AC Design Considerations
High speed current-feed amplifiers are sensitive to
capacitance at the inverting input and output terminals.
Capacitance at the output terminal increases gain peaking
and overshoot. The AC response of the ISL59451 is
optimized for a total output capacitance of 2.1pF with a load
of 150Ω (Figure 35A). When PCB trace capacitance and
component capacitance exceed 2pF, overshoot becomes
strongly dependent on the input pulse amplitude and slew
rate. Increasing levels of output capacitance reduce stability,
resulting in increased overshoot and settling time.
PC board trace length (L_CRIT) should be kept to a minimum
in order to minimize output capacitance. At 500MHz, trace
lengths approaching 1” begin exhibiting transmission line
behavior and may cause excessive ringing if controlled
impedance traces are not used. Figure 35B shows the
optimum inter-stage circuit when the total output trace length
is less than the critical length of the highest signal frequency.
As a general rule of thumb the trace lengths should be less
than one-tenth of the wavelength of the highest frequency
component in the signal. Equation 6 shows an approximate
way to calculate L_CRIT in meters.
L_C
R
IT
≤
---------------------^c----------------------
10 × f_MAX × ε_R
(EQ. 6)
c = speed of light (3 x 10^8 m/s)
f_MAX = maximum frequency component
ε_R = relative dielectric of board material (e.g. FR4 = 4.2)
For applications where inter-stage distances are long but
pulse response is not critical, capacitor C_S can be added to
low values of R_S to form a low-pass filter to dampen pulse
overshoot. This approach avoids the need for the large gain
correction required by the -6dB attenuation of the
back-loaded controlled impedance interconnect. Load
resistor R_L is still required but can be 500Ω or greater,
resulting in a much smaller attenuation factor.
For applications where pulse response is critical and where
inter-stage distances exceed L_CRIT, the circuit shown in
Figure 35C is recommended. Resistor R_S constrains the
capacitance seen by the amplifier output to the trace
capacitance betweeen the output pin and the resistor.
Therefore, R_S should be placed as close to the ISL59451
output pin as possible. For inter-stage distances much greater
than L_CRIT, the back-loaded circuit shown in Figure 35D
should be used with controlled impedance PCB lines, with R_S
and R_L equal to the controlled impedance.
Control Signals
S0, S1, HIZ, CLAMP, and AV2 are binary coded, TTL/CMOS
compatible control inputs. The S0, S1 pins select the inputs.
All three amplifiers are switched simultaneously from their
respective inputs. When HIZ is pulled high, it puts the outputs
in a high-impedance state and disconnects the video inputs.
15
FN6253.0
September 24, 2007