X28C010KM-25 Datasheet, PDF (14/20 Pages) Intersil Corporation – Protects data against system level inadvertent writes

Page Write Cycle
OE ^{(Note 5)}
X28C010, X28HT010
CE
t_WP
WE
Address* ^{(Note 7)}
t_WPH
t_BLC
I/O
Last Byte
Byte 0
Byte 1
Byte 2
Byte n
Byte n+1
*For each successive write within the page write operation, A₈-A₁₆ should be the same or
writes to an unknown address could occur.
Byte n+2
t_WC
NOTES:
6. Between successive byte writes within a page write operation, OE can be strobed LOW: e.g. this can be done with CE and WE HIGH to fetch
data from another memory device within the system for the next write; or with WE HIGH and CE LOW effectively performing a polling operation.
7. The timings shown above are unique to page write operations. Individual byte load operations within the page write must conform to either the
CE or WE controlled write cycle timing.
DATA Polling Timing Diagram (Note 8)
Address
A_n
A_n
A_n
CE
WE
t_OEH
OE
I/O₇
D_IN = X
D_OUT = X
t_WC
t_OES
t_DW
D_OUT = X
14
FN8105.1
February 12, 2007